273 lines · yaml
1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A10 Display Engine Backend8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13description: |14 The display engine backend exposes layers and sprites to the system.15 16properties:17 compatible:18 enum:19 - allwinner,sun4i-a10-display-backend20 - allwinner,sun5i-a13-display-backend21 - allwinner,sun6i-a31-display-backend22 - allwinner,sun7i-a20-display-backend23 - allwinner,sun8i-a23-display-backend24 - allwinner,sun8i-a33-display-backend25 - allwinner,sun9i-a80-display-backend26 27 reg:28 minItems: 129 items:30 - description: Display Backend registers31 - description: SAT registers32 33 reg-names:34 minItems: 135 items:36 - const: be37 - const: sat38 39 interrupts:40 maxItems: 141 42 clocks:43 minItems: 344 items:45 - description: The backend interface clock46 - description: The backend module clock47 - description: The backend DRAM clock48 - description: The SAT clock49 50 clock-names:51 minItems: 352 items:53 - const: ahb54 - const: mod55 - const: ram56 - const: sat57 58 resets:59 minItems: 160 items:61 - description: The Backend reset line62 - description: The SAT reset line63 64 reset-names:65 minItems: 166 items:67 - const: be68 - const: sat69 70 # FIXME: This should be made required eventually once every SoC will71 # have the MBUS declared.72 interconnects:73 maxItems: 174 75 # FIXME: This should be made required eventually once every SoC will76 # have the MBUS declared.77 interconnect-names:78 const: dma-mem79 80 ports:81 $ref: /schemas/graph.yaml#/properties/ports82 83 properties:84 port@0:85 $ref: /schemas/graph.yaml#/properties/port86 description:87 Input endpoints of the controller.88 89 port@1:90 $ref: /schemas/graph.yaml#/properties/port91 description:92 Output endpoints of the controller.93 94 required:95 - port@096 - port@197 98required:99 - compatible100 - reg101 - interrupts102 - clocks103 - clock-names104 - resets105 - ports106 107additionalProperties: false108 109if:110 properties:111 compatible:112 contains:113 const: allwinner,sun8i-a33-display-backend114 115then:116 properties:117 reg:118 minItems: 2119 120 reg-names:121 minItems: 2122 123 clocks:124 minItems: 4125 126 clock-names:127 minItems: 4128 129 resets:130 minItems: 2131 132 reset-names:133 minItems: 2134 135 required:136 - reg-names137 - reset-names138 139else:140 properties:141 reg:142 maxItems: 1143 144 reg-names:145 maxItems: 1146 147 clocks:148 maxItems: 3149 150 clock-names:151 maxItems: 3152 153 resets:154 maxItems: 1155 156 reset-names:157 maxItems: 1158 159examples:160 - |161 /*162 * This comes from the clock/sun4i-a10-ccu.h and163 * reset/sun4i-a10-ccu.h headers, but we can't include them since164 * it would trigger a bunch of warnings for redefinitions of165 * symbols with the other example.166 */167 168 #define CLK_AHB_DE_BE0 42169 #define CLK_DRAM_DE_BE0 140170 #define CLK_DE_BE0 144171 #define RST_DE_BE0 5172 173 display-backend@1e60000 {174 compatible = "allwinner,sun4i-a10-display-backend";175 reg = <0x01e60000 0x10000>;176 interrupts = <47>;177 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,178 <&ccu CLK_DRAM_DE_BE0>;179 clock-names = "ahb", "mod",180 "ram";181 resets = <&ccu RST_DE_BE0>;182 183 ports {184 #address-cells = <1>;185 #size-cells = <0>;186 187 port@0 {188 #address-cells = <1>;189 #size-cells = <0>;190 reg = <0>;191 192 endpoint@0 {193 reg = <0>;194 remote-endpoint = <&fe0_out_be0>;195 };196 197 endpoint@1 {198 reg = <1>;199 remote-endpoint = <&fe1_out_be0>;200 };201 };202 203 port@1 {204 #address-cells = <1>;205 #size-cells = <0>;206 reg = <1>;207 208 endpoint@0 {209 reg = <0>;210 remote-endpoint = <&tcon0_in_be0>;211 };212 213 endpoint@1 {214 reg = <1>;215 remote-endpoint = <&tcon1_in_be0>;216 };217 };218 };219 };220 221 - |222 #include <dt-bindings/interrupt-controller/arm-gic.h>223 224 /*225 * This comes from the clock/sun8i-a23-a33-ccu.h and226 * reset/sun8i-a23-a33-ccu.h headers, but we can't include them227 * since it would trigger a bunch of warnings for redefinitions of228 * symbols with the other example.229 */230 231 #define CLK_BUS_DE_BE 40232 #define CLK_BUS_SAT 46233 #define CLK_DRAM_DE_BE 84234 #define CLK_DE_BE 85235 #define RST_BUS_DE_BE 21236 #define RST_BUS_SAT 27237 238 display-backend@1e60000 {239 compatible = "allwinner,sun8i-a33-display-backend";240 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;241 reg-names = "be", "sat";242 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;243 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,244 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;245 clock-names = "ahb", "mod",246 "ram", "sat";247 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;248 reset-names = "be", "sat";249 250 ports {251 #address-cells = <1>;252 #size-cells = <0>;253 254 port@0 {255 reg = <0>;256 257 endpoint {258 remote-endpoint = <&fe0_out_be0>;259 };260 };261 262 port@1 {263 reg = <1>;264 265 endpoint {266 remote-endpoint = <&drc0_in_be0>;267 };268 };269 };270 };271 272...273