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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A83t DWC HDMI TX Encoder8 9description: |10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller11 IP with Allwinner\'s own PHY IP. It supports audio and video outputs12 and CEC.13 14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific16 properties.17 18maintainers:19 - Chen-Yu Tsai <wens@csie.org>20 - Maxime Ripard <mripard@kernel.org>21 22properties:23 "#phy-cells":24 const: 025 26 compatible:27 oneOf:28 - const: allwinner,sun8i-a83t-dw-hdmi29 - const: allwinner,sun50i-h6-dw-hdmi30 31 - items:32 - enum:33 - allwinner,sun8i-h3-dw-hdmi34 - allwinner,sun8i-r40-dw-hdmi35 - allwinner,sun50i-a64-dw-hdmi36 - const: allwinner,sun8i-a83t-dw-hdmi37 38 reg:39 maxItems: 140 41 reg-io-width:42 const: 143 44 interrupts:45 maxItems: 146 47 clocks:48 minItems: 349 items:50 - description: Bus Clock51 - description: Register Clock52 - description: TMDS Clock53 - description: HDMI CEC Clock54 - description: HDCP Clock55 - description: HDCP Bus Clock56 57 clock-names:58 minItems: 359 items:60 - const: iahb61 - const: isfr62 - const: tmds63 - const: cec64 - const: hdcp65 - const: hdcp-bus66 67 resets:68 minItems: 169 items:70 - description: HDMI Controller Reset71 - description: HDCP Reset72 73 reset-names:74 minItems: 175 items:76 - const: ctrl77 - const: hdcp78 79 phys:80 maxItems: 181 description:82 Phandle to the DWC HDMI PHY.83 84 phy-names:85 const: phy86 87 hvcc-supply:88 description:89 The VCC power supply of the controller90 91 ports:92 $ref: /schemas/graph.yaml#/properties/ports93 94 properties:95 port@0:96 $ref: /schemas/graph.yaml#/properties/port97 description: |98 Input endpoints of the controller. Usually the associated99 TCON.100 101 port@1:102 $ref: /schemas/graph.yaml#/properties/port103 description: |104 Output endpoints of the controller. Usually an HDMI105 connector.106 107 required:108 - port@0109 - port@1110 111required:112 - compatible113 - reg114 - reg-io-width115 - interrupts116 - clocks117 - clock-names118 - resets119 - reset-names120 - phys121 - phy-names122 - ports123 124if:125 properties:126 compatible:127 contains:128 enum:129 - allwinner,sun50i-h6-dw-hdmi130 131then:132 properties:133 clocks:134 minItems: 6135 136 clock-names:137 minItems: 6138 139 resets:140 minItems: 2141 142 reset-names:143 minItems: 2144 145 146additionalProperties: false147 148examples:149 - |150 #include <dt-bindings/interrupt-controller/arm-gic.h>151 152 /*153 * This comes from the clock/sun8i-a83t-ccu.h and154 * reset/sun8i-a83t-ccu.h headers, but we can't include them since155 * it would trigger a bunch of warnings for redefinitions of156 * symbols with the other example.157 */158 #define CLK_BUS_HDMI 39159 #define CLK_HDMI 93160 #define CLK_HDMI_SLOW 94161 #define RST_BUS_HDMI1 26162 163 hdmi@1ee0000 {164 compatible = "allwinner,sun8i-a83t-dw-hdmi";165 reg = <0x01ee0000 0x10000>;166 reg-io-width = <1>;167 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;168 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,169 <&ccu CLK_HDMI>;170 clock-names = "iahb", "isfr", "tmds";171 resets = <&ccu RST_BUS_HDMI1>;172 reset-names = "ctrl";173 phys = <&hdmi_phy>;174 phy-names = "phy";175 pinctrl-names = "default";176 pinctrl-0 = <&hdmi_pins>;177 178 ports {179 #address-cells = <1>;180 #size-cells = <0>;181 182 port@0 {183 reg = <0>;184 185 endpoint {186 remote-endpoint = <&tcon1_out_hdmi>;187 };188 };189 190 port@1 {191 reg = <1>;192 };193 };194 };195 196 /* Cleanup after ourselves */197 #undef CLK_BUS_HDMI198 #undef CLK_HDMI199 #undef CLK_HDMI_SLOW200 201 - |202 #include <dt-bindings/interrupt-controller/arm-gic.h>203 204 /*205 * This comes from the clock/sun50i-h6-ccu.h and206 * reset/sun50i-h6-ccu.h headers, but we can't include them since207 * it would trigger a bunch of warnings for redefinitions of208 * symbols with the other example.209 */210 #define CLK_BUS_HDMI 126211 #define CLK_BUS_HDCP 137212 #define CLK_HDMI 123213 #define CLK_HDMI_SLOW 124214 #define CLK_HDMI_CEC 125215 #define CLK_HDCP 136216 #define RST_BUS_HDMI_SUB 57217 #define RST_BUS_HDCP 62218 219 hdmi@6000000 {220 compatible = "allwinner,sun50i-h6-dw-hdmi";221 reg = <0x06000000 0x10000>;222 reg-io-width = <1>;223 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;224 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,225 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,226 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;227 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",228 "hdcp-bus";229 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;230 reset-names = "ctrl", "hdcp";231 phys = <&hdmi_phy>;232 phy-names = "phy";233 pinctrl-names = "default";234 pinctrl-0 = <&hdmi_pins>;235 236 ports {237 #address-cells = <1>;238 #size-cells = <0>;239 240 port@0 {241 reg = <0>;242 243 endpoint {244 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;245 };246 };247 248 port@1 {249 reg = <1>;250 };251 };252 };253 254...255