brintos

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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A83t HDMI PHY8 9maintainers:10  - Chen-Yu Tsai <wens@csie.org>11  - Maxime Ripard <mripard@kernel.org>12 13properties:14  "#phy-cells":15    const: 016 17  compatible:18    enum:19      - allwinner,sun8i-a83t-hdmi-phy20      - allwinner,sun8i-h3-hdmi-phy21      - allwinner,sun8i-r40-hdmi-phy22      - allwinner,sun50i-a64-hdmi-phy23      - allwinner,sun50i-h6-hdmi-phy24 25  reg:26    maxItems: 127 28  clocks:29    minItems: 230    items:31      - description: Bus Clock32      - description: Module Clock33      - description: Parent of the PHY clock34      - description: Second possible parent of the PHY clock35 36  clock-names:37    minItems: 238    items:39      - const: bus40      - const: mod41      - const: pll-042      - const: pll-143 44  resets:45    maxItems: 146 47  reset-names:48    const: phy49 50required:51  - compatible52  - reg53  - clocks54  - clock-names55  - resets56  - reset-names57 58if:59  properties:60    compatible:61      contains:62        enum:63          - allwinner,sun8i-r40-hdmi-phy64 65then:66  properties:67    clocks:68      minItems: 469 70    clock-names:71      minItems: 472 73else:74  if:75    properties:76      compatible:77        contains:78          enum:79            - allwinner,sun8i-h3-hdmi-phy80            - allwinner,sun50i-a64-hdmi-phy81 82  then:83    properties:84      clocks:85        minItems: 386 87      clock-names:88        minItems: 389 90  else:91    properties:92      clocks:93        maxItems: 294 95      clock-names:96        maxItems: 297 98additionalProperties: false99 100examples:101  - |102    #include <dt-bindings/clock/sun8i-a83t-ccu.h>103    #include <dt-bindings/reset/sun8i-a83t-ccu.h>104 105    hdmi_phy: hdmi-phy@1ef0000 {106        compatible = "allwinner,sun8i-a83t-hdmi-phy";107        reg = <0x01ef0000 0x10000>;108        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;109        clock-names = "bus", "mod";110        resets = <&ccu RST_BUS_HDMI0>;111        reset-names = "phy";112        #phy-cells = <0>;113    };114 115...116