86 lines · yaml
1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Broadcom VC4 (VideoCore4) DSI Controller8 9maintainers:10 - Eric Anholt <eric@anholt.net>11 12allOf:13 - $ref: dsi-controller.yaml#14 15properties:16 "#clock-cells":17 const: 118 19 compatible:20 enum:21 - brcm,bcm2711-dsi122 - brcm,bcm2835-dsi023 - brcm,bcm2835-dsi124 25 reg:26 maxItems: 127 28 clocks:29 items:30 - description: The DSI PLL clock feeding the DSI analog PHY31 - description: The DSI ESC clock32 - description: The DSI pixel clock33 34 clock-names:35 items:36 - const: phy37 - const: escape38 - const: pixel39 40 clock-output-names: true41 # FIXME: The meta-schemas don't seem to allow it for now42 # items:43 # - description: The DSI byte clock for the PHY44 # - description: The DSI DDR2 clock45 # - description: The DSI DDR clock46 47 interrupts:48 maxItems: 149 50 power-domains:51 maxItems: 152 53required:54 - "#clock-cells"55 - compatible56 - reg57 - clocks58 - clock-names59 - clock-output-names60 - interrupts61 62unevaluatedProperties: false63 64examples:65 - |66 #include <dt-bindings/clock/bcm2835.h>67 68 dsi1: dsi@7e700000 {69 compatible = "brcm,bcm2835-dsi1";70 reg = <0x7e700000 0x8c>;71 interrupts = <2 12>;72 #address-cells = <1>;73 #size-cells = <0>;74 #clock-cells = <1>;75 76 clocks = <&clocks BCM2835_PLLD_DSI1>,77 <&clocks BCM2835_CLOCK_DSI1E>,78 <&clocks BCM2835_CLOCK_DSI1P>;79 clock-names = "phy", "escape", "pixel";80 81 clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";82 83 };84 85...86