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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MX8qm/qxp Pixel Combiner8 9maintainers:10 - Liu Ying <victor.liu@nxp.com>11 12description: |13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a14 single display controller and manipulates the two streams to support a number15 of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as16 either one screen, two screens, or virtual screens. The pixel combiner is17 also responsible for generating some of the control signals for the pixel link18 output channel.19 20properties:21 compatible:22 enum:23 - fsl,imx8qm-pixel-combiner24 - fsl,imx8qxp-pixel-combiner25 26 "#address-cells":27 const: 128 29 "#size-cells":30 const: 031 32 reg:33 maxItems: 134 35 clocks:36 maxItems: 137 38 clock-names:39 const: apb40 41 power-domains:42 maxItems: 143 44patternProperties:45 "^channel@[0-1]$":46 type: object47 description: Represents a display stream of pixel combiner.48 49 properties:50 "#address-cells":51 const: 152 53 "#size-cells":54 const: 055 56 reg:57 description: The display stream index.58 enum: [ 0, 1 ]59 60 port@0:61 $ref: /schemas/graph.yaml#/properties/port62 description: Input endpoint of the display stream.63 64 port@1:65 $ref: /schemas/graph.yaml#/properties/port66 description: Output endpoint of the display stream.67 68 required:69 - "#address-cells"70 - "#size-cells"71 - reg72 - port@073 - port@174 75 additionalProperties: false76 77required:78 - compatible79 - "#address-cells"80 - "#size-cells"81 - reg82 - clocks83 - clock-names84 - power-domains85 86additionalProperties: false87 88examples:89 - |90 #include <dt-bindings/clock/imx8-lpcg.h>91 #include <dt-bindings/firmware/imx/rsrc.h>92 pixel-combiner@56020000 {93 compatible = "fsl,imx8qxp-pixel-combiner";94 #address-cells = <1>;95 #size-cells = <0>;96 reg = <0x56020000 0x10000>;97 clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;98 clock-names = "apb";99 power-domains = <&pd IMX_SC_R_DC_0>;100 101 channel@0 {102 #address-cells = <1>;103 #size-cells = <0>;104 reg = <0>;105 106 port@0 {107 reg = <0>;108 109 dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {110 remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;111 };112 };113 114 port@1 {115 reg = <1>;116 117 dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {118 remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;119 };120 };121 };122 123 channel@1 {124 #address-cells = <1>;125 #size-cells = <0>;126 reg = <1>;127 128 port@0 {129 reg = <0>;130 131 dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {132 remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;133 };134 };135 136 port@1 {137 reg = <1>;138 139 dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {140 remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;141 };142 };143 };144 };145