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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Northwest Logic MIPI-DSI controller on i.MX SoCs8 9maintainers:10 - Guido Gúnther <agx@sigxcpu.org>11 - Robert Chiras <robert.chiras@nxp.com>12 13description: |14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for15 the SOCs NWL MIPI-DSI host controller.16 17allOf:18 - $ref: ../dsi-controller.yaml#19 20properties:21 compatible:22 const: fsl,imx8mq-nwl-dsi23 24 reg:25 maxItems: 126 27 interrupts:28 maxItems: 129 30 '#address-cells':31 const: 132 33 '#size-cells':34 const: 035 36 assigned-clock-parents: true37 assigned-clock-rates: true38 assigned-clocks: true39 40 clocks:41 items:42 - description: DSI core clock43 - description: RX_ESC clock (used in escape mode)44 - description: TX_ESC clock (used in escape mode)45 - description: PHY_REF clock46 - description: LCDIF clock47 48 clock-names:49 items:50 - const: core51 - const: rx_esc52 - const: tx_esc53 - const: phy_ref54 - const: lcdif55 56 mux-controls:57 description:58 mux controller node to use for operating the input mux59 60 phys:61 maxItems: 162 description:63 A phandle to the phy module representing the DPHY64 65 phy-names:66 items:67 - const: dphy68 69 power-domains:70 maxItems: 171 72 resets:73 items:74 - description: dsi byte reset line75 - description: dsi dpi reset line76 - description: dsi esc reset line77 - description: dsi pclk reset line78 79 reset-names:80 items:81 - const: byte82 - const: dpi83 - const: esc84 - const: pclk85 86 ports:87 $ref: /schemas/graph.yaml#/properties/ports88 89 properties:90 port@0:91 $ref: /schemas/graph.yaml#/$defs/port-base92 description:93 Input port node to receive pixel data from the94 display controller. Exactly one endpoint must be95 specified.96 properties:97 endpoint@0:98 $ref: /schemas/graph.yaml#/properties/endpoint99 description: sub-node describing the input from LCDIF100 101 endpoint@1:102 $ref: /schemas/graph.yaml#/properties/endpoint103 description: sub-node describing the input from DCSS104 105 oneOf:106 - required:107 - endpoint@0108 - required:109 - endpoint@1110 111 unevaluatedProperties: false112 113 port@1:114 $ref: /schemas/graph.yaml#/properties/port115 description:116 DSI output port node to the panel or the next bridge117 in the chain118 119 required:120 - port@0121 - port@1122 123required:124 - '#address-cells'125 - '#size-cells'126 - clock-names127 - clocks128 - compatible129 - interrupts130 - mux-controls131 - phy-names132 - phys133 - ports134 - reg135 - reset-names136 - resets137 138unevaluatedProperties: false139 140examples:141 - |142 #include <dt-bindings/clock/imx8mq-clock.h>143 #include <dt-bindings/gpio/gpio.h>144 #include <dt-bindings/interrupt-controller/arm-gic.h>145 #include <dt-bindings/reset/imx8mq-reset.h>146 147 dsi@30a00000 {148 #address-cells = <1>;149 #size-cells = <0>;150 compatible = "fsl,imx8mq-nwl-dsi";151 reg = <0x30A00000 0x300>;152 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,153 <&clk IMX8MQ_CLK_DSI_AHB>,154 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,155 <&clk IMX8MQ_CLK_DSI_PHY_REF>,156 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;157 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";158 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;159 mux-controls = <&mux 0>;160 power-domains = <&pgc_mipi>;161 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,162 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,163 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,164 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;165 reset-names = "byte", "dpi", "esc", "pclk";166 phys = <&dphy>;167 phy-names = "dphy";168 169 panel@0 {170 compatible = "rocktech,jh057n00900";171 reg = <0>;172 vcc-supply = <®_2v8_p>;173 iovcc-supply = <®_1v8_p>;174 reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;175 port {176 panel_in: endpoint {177 remote-endpoint = <&mipi_dsi_out>;178 };179 };180 };181 182 ports {183 #address-cells = <1>;184 #size-cells = <0>;185 186 port@0 {187 #size-cells = <0>;188 #address-cells = <1>;189 reg = <0>;190 mipi_dsi_in: endpoint@0 {191 reg = <0>;192 remote-endpoint = <&lcdif_mipi_dsi>;193 };194 };195 port@1 {196 reg = <1>;197 mipi_dsi_out: endpoint {198 remote-endpoint = <&panel_in>;199 };200 };201 };202 };203