281 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Samsung MIPI DSIM bridge controller8 9maintainers:10 - Inki Dae <inki.dae@samsung.com>11 - Jagan Teki <jagan@amarulasolutions.com>12 - Marek Szyprowski <m.szyprowski@samsung.com>13 14description: |15 Samsung MIPI DSIM bridge controller can be found it on Exynos16 and i.MX8M Mini/Nano/Plus SoC's.17 18properties:19 compatible:20 oneOf:21 - enum:22 - samsung,exynos3250-mipi-dsi23 - samsung,exynos4210-mipi-dsi24 - samsung,exynos5410-mipi-dsi25 - samsung,exynos5422-mipi-dsi26 - samsung,exynos5433-mipi-dsi27 - fsl,imx8mm-mipi-dsim28 - fsl,imx8mp-mipi-dsim29 - items:30 - const: fsl,imx8mn-mipi-dsim31 - const: fsl,imx8mm-mipi-dsim32 33 reg:34 maxItems: 135 36 interrupts:37 maxItems: 138 39 '#address-cells':40 const: 141 42 '#size-cells':43 const: 044 45 clocks:46 minItems: 247 maxItems: 548 49 clock-names:50 minItems: 251 maxItems: 552 53 samsung,phy-type:54 $ref: /schemas/types.yaml#/definitions/uint3255 description: phandle to the samsung phy-type56 57 power-domains:58 maxItems: 159 60 samsung,power-domain:61 $ref: /schemas/types.yaml#/definitions/phandle62 description: phandle to the associated samsung power domain63 64 vddcore-supply:65 description: MIPI DSIM Core voltage supply (e.g. 1.1V)66 67 vddio-supply:68 description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)69 70 samsung,burst-clock-frequency:71 $ref: /schemas/types.yaml#/definitions/uint3272 description:73 DSIM high speed burst mode frequency. If absent,74 the pixel clock from the attached device or bridge75 will be used instead.76 77 samsung,esc-clock-frequency:78 $ref: /schemas/types.yaml#/definitions/uint3279 description:80 DSIM escape mode frequency.81 82 samsung,pll-clock-frequency:83 $ref: /schemas/types.yaml#/definitions/uint3284 description:85 DSIM oscillator clock frequency. If absent, the clock frequency86 of sclk_mipi will be used instead.87 88 phys:89 maxItems: 190 91 phy-names:92 const: dsim93 94 ports:95 $ref: /schemas/graph.yaml#/properties/ports96 97 properties:98 port@0:99 $ref: /schemas/graph.yaml#/properties/port100 description:101 Input port node to receive pixel data from the102 display controller. Exactly one endpoint must be103 specified.104 105 port@1:106 $ref: /schemas/graph.yaml#/$defs/port-base107 unevaluatedProperties: false108 description:109 DSI output port node to the panel or the next bridge110 in the chain.111 112 properties:113 endpoint:114 $ref: /schemas/media/video-interfaces.yaml#115 unevaluatedProperties: false116 117 properties:118 data-lanes:119 minItems: 1120 maxItems: 4121 uniqueItems: true122 items:123 enum: [ 1, 2, 3, 4 ]124 125 lane-polarities:126 minItems: 1127 maxItems: 5128 description:129 The Samsung MIPI DSI IP requires that all the data lanes have130 the same polarity.131 132 dependencies:133 lane-polarities: [data-lanes]134 135required:136 - clock-names137 - clocks138 - compatible139 - interrupts140 - reg141 - samsung,esc-clock-frequency142 143allOf:144 - $ref: ../dsi-controller.yaml#145 - if:146 properties:147 compatible:148 contains:149 const: samsung,exynos5433-mipi-dsi150 151 then:152 properties:153 clocks:154 minItems: 5155 156 clock-names:157 items:158 - const: bus_clk159 - const: phyclk_mipidphy0_bitclkdiv8160 - const: phyclk_mipidphy0_rxclkesc0161 - const: sclk_rgb_vclk_to_dsim0162 - const: sclk_mipi163 164 ports:165 required:166 - port@0167 168 required:169 - ports170 - vddcore-supply171 - vddio-supply172 173 - if:174 properties:175 compatible:176 contains:177 const: samsung,exynos5410-mipi-dsi178 179 then:180 properties:181 clocks:182 minItems: 2183 184 clock-names:185 items:186 - const: bus_clk187 - const: pll_clk188 189 required:190 - vddcore-supply191 - vddio-supply192 193 - if:194 properties:195 compatible:196 contains:197 const: samsung,exynos4210-mipi-dsi198 199 then:200 properties:201 clocks:202 minItems: 2203 204 clock-names:205 items:206 - const: bus_clk207 - const: sclk_mipi208 209 required:210 - vddcore-supply211 - vddio-supply212 213 - if:214 properties:215 compatible:216 contains:217 const: samsung,exynos3250-mipi-dsi218 219 then:220 properties:221 clocks:222 minItems: 2223 224 clock-names:225 items:226 - const: bus_clk227 - const: pll_clk228 229 required:230 - vddcore-supply231 - vddio-supply232 - samsung,phy-type233 234additionalProperties:235 type: object236 237examples:238 - |239 #include <dt-bindings/clock/exynos5433.h>240 #include <dt-bindings/gpio/gpio.h>241 #include <dt-bindings/interrupt-controller/arm-gic.h>242 243 dsi@13900000 {244 compatible = "samsung,exynos5433-mipi-dsi";245 reg = <0x13900000 0xC0>;246 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;247 phys = <&mipi_phy 1>;248 phy-names = "dsim";249 clocks = <&cmu_disp CLK_PCLK_DSIM0>,250 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,251 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,252 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,253 <&cmu_disp CLK_SCLK_DSIM0>;254 clock-names = "bus_clk",255 "phyclk_mipidphy0_bitclkdiv8",256 "phyclk_mipidphy0_rxclkesc0",257 "sclk_rgb_vclk_to_dsim0",258 "sclk_mipi";259 power-domains = <&pd_disp>;260 vddcore-supply = <&ldo6_reg>;261 vddio-supply = <&ldo7_reg>;262 samsung,burst-clock-frequency = <512000000>;263 samsung,esc-clock-frequency = <16000000>;264 samsung,pll-clock-frequency = <24000000>;265 pinctrl-names = "default";266 pinctrl-0 = <&te_irq>;267 268 ports {269 #address-cells = <1>;270 #size-cells = <0>;271 272 port@0 {273 reg = <0>;274 275 dsi_to_mic: endpoint {276 remote-endpoint = <&mic_to_dsi>;277 };278 };279 };280 };281