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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/lvds-data-mapping.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: LVDS Data Mapping8 9maintainers:10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>11 - Thierry Reding <thierry.reding@gmail.com>12 13description: |14 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple15 incompatible data link layers have been used over time to transmit image data16 to LVDS devices. This bindings supports devices compatible with the following17 specifications.18 19 [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February20 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)21 [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National22 Semiconductor23 [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video24 Electronics Standards Association (VESA)25 26 Device compatible with those specifications have been marketed under the27 FPD-Link and FlatLink brands.28 29properties:30 data-mapping:31 enum:32 - jeida-1833 - jeida-2434 - vesa-2435 description: |36 The color signals mapping order.37 38 LVDS data mappings are defined as follows.39 40 - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and41 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.42 43 Slot 0 1 2 3 4 5 644 ________________ _________________45 Clock \_______________________/46 ______ ______ ______ ______ ______ ______ ______47 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><48 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><49 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><50 51 - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]52 specifications. Data are transferred as follows on 4 LVDS lanes.53 54 Slot 0 1 2 3 4 5 655 ________________ _________________56 Clock \_______________________/57 ______ ______ ______ ______ ______ ______ ______58 DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><59 DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><60 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><61 DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><62 63 - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.64 Data are transferred as follows on 4 LVDS lanes.65 66 Slot 0 1 2 3 4 5 667 ________________ _________________68 Clock \_______________________/69 ______ ______ ______ ______ ______ ______ ______70 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><71 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><72 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><73 DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><74 75 Control signals are mapped as follows.76 77 CTL0: HSync78 CTL1: VSync79 CTL2: Data Enable80 CTL3: 081 82additionalProperties: true83 84...85