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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek DSI Controller8 9maintainers:10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>11 - Philipp Zabel <p.zabel@pengutronix.de>12 - Jitao Shi <jitao.shi@mediatek.com>13 14description: |15 The MediaTek DSI function block is a sink of the display subsystem and can16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-17 channel output.18 19allOf:20 - $ref: /schemas/display/dsi-controller.yaml#21 22properties:23 compatible:24 oneOf:25 - enum:26 - mediatek,mt2701-dsi27 - mediatek,mt7623-dsi28 - mediatek,mt8167-dsi29 - mediatek,mt8173-dsi30 - mediatek,mt8183-dsi31 - mediatek,mt8186-dsi32 - mediatek,mt8188-dsi33 - items:34 - enum:35 - mediatek,mt6795-dsi36 - const: mediatek,mt8173-dsi37 - items:38 - enum:39 - mediatek,mt8195-dsi40 - mediatek,mt8365-dsi41 - const: mediatek,mt8183-dsi42 43 reg:44 maxItems: 145 46 interrupts:47 maxItems: 148 49 power-domains:50 maxItems: 151 52 clocks:53 items:54 - description: Engine Clock55 - description: Digital Clock56 - description: HS Clock57 58 clock-names:59 items:60 - const: engine61 - const: digital62 - const: hs63 64 resets:65 maxItems: 166 67 phys:68 maxItems: 169 70 phy-names:71 items:72 - const: dphy73 74 port:75 $ref: /schemas/graph.yaml#/properties/port76 description:77 Output port node. This port should be connected to the input78 port of an attached DSI panel or DSI-to-eDP encoder chip.79 80required:81 - compatible82 - reg83 - interrupts84 - power-domains85 - clocks86 - clock-names87 - phys88 - phy-names89 - port90 91unevaluatedProperties: false92 93examples:94 - |95 #include <dt-bindings/clock/mt8183-clk.h>96 #include <dt-bindings/interrupt-controller/arm-gic.h>97 #include <dt-bindings/interrupt-controller/irq.h>98 #include <dt-bindings/power/mt8183-power.h>99 #include <dt-bindings/phy/phy.h>100 #include <dt-bindings/reset/mt8183-resets.h>101 102 soc {103 #address-cells = <2>;104 #size-cells = <2>;105 106 dsi0: dsi@14014000 {107 compatible = "mediatek,mt8183-dsi";108 reg = <0 0x14014000 0 0x1000>;109 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;110 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;111 clocks = <&mmsys CLK_MM_DSI0_MM>,112 <&mmsys CLK_MM_DSI0_IF>,113 <&mipi_tx0>;114 clock-names = "engine", "digital", "hs";115 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;116 phys = <&mipi_tx0>;117 phy-names = "dphy";118 port {119 dsi0_out: endpoint {120 remote-endpoint = <&panel_in>;121 };122 };123 };124 };125 126...127