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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek Ethdr Device8 9maintainers:10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>11 - Philipp Zabel <p.zabel@pengutronix.de>12 13description:14 ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is15 designed for HDR video and graphics conversion in the external display path.16 It handles multiple HDR input types and performs tone mapping, color17 space/color format conversion, and then combine different layers,18 output the required HDR or SDR signal to the subsequent display path.19 This engine is composed of two video frontends, two graphic frontends,20 one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.21 These two function blocks read the pre-programmed registers from DRAM and22 set them to HW in the v-blanking period.23 24properties:25 compatible:26 oneOf:27 - const: mediatek,mt8195-disp-ethdr28 - items:29 - const: mediatek,mt8188-disp-ethdr30 - const: mediatek,mt8195-disp-ethdr31 32 reg:33 maxItems: 734 35 reg-names:36 items:37 - const: mixer38 - const: vdo_fe039 - const: vdo_fe140 - const: gfx_fe041 - const: gfx_fe142 - const: vdo_be43 - const: adl_ds44 45 interrupts:46 maxItems: 147 48 iommus:49 minItems: 150 maxItems: 251 52 clocks:53 items:54 - description: mixer clock55 - description: video frontend 0 clock56 - description: video frontend 1 clock57 - description: graphic frontend 0 clock58 - description: graphic frontend 1 clock59 - description: video backend clock60 - description: autodownload and menuload clock61 - description: video frontend 0 async clock62 - description: video frontend 1 async clock63 - description: graphic frontend 0 async clock64 - description: graphic frontend 1 async clock65 - description: video backend async clock66 - description: ethdr top clock67 68 clock-names:69 items:70 - const: mixer71 - const: vdo_fe072 - const: vdo_fe173 - const: gfx_fe074 - const: gfx_fe175 - const: vdo_be76 - const: adl_ds77 - const: vdo_fe0_async78 - const: vdo_fe1_async79 - const: gfx_fe0_async80 - const: gfx_fe1_async81 - const: vdo_be_async82 - const: ethdr_top83 84 power-domains:85 maxItems: 186 87 resets:88 items:89 - description: video frontend 0 async reset90 - description: video frontend 1 async reset91 - description: graphic frontend 0 async reset92 - description: graphic frontend 1 async reset93 - description: video backend async reset94 95 reset-names:96 items:97 - const: vdo_fe0_async98 - const: vdo_fe1_async99 - const: gfx_fe0_async100 - const: gfx_fe1_async101 - const: vdo_be_async102 103 mediatek,gce-client-reg:104 $ref: /schemas/types.yaml#/definitions/phandle-array105 minItems: 1106 maxItems: 7107 description: The register of display function block to be set by gce.108 There are 4 arguments in this property, gce node, subsys id, offset and109 register size. The subsys id is defined in the gce header of each chips110 include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display111 function block.112 113required:114 - compatible115 - reg116 - clocks117 - clock-names118 - interrupts119 - power-domains120 - resets121 - mediatek,gce-client-reg122 123additionalProperties: false124 125examples:126 - |127 #include <dt-bindings/interrupt-controller/arm-gic.h>128 #include <dt-bindings/clock/mt8195-clk.h>129 #include <dt-bindings/gce/mt8195-gce.h>130 #include <dt-bindings/memory/mt8195-memory-port.h>131 #include <dt-bindings/power/mt8195-power.h>132 #include <dt-bindings/reset/mt8195-resets.h>133 134 soc {135 #address-cells = <2>;136 #size-cells = <2>;137 138 hdr-engine@1c114000 {139 compatible = "mediatek,mt8195-disp-ethdr";140 reg = <0 0x1c114000 0 0x1000>,141 <0 0x1c115000 0 0x1000>,142 <0 0x1c117000 0 0x1000>,143 <0 0x1c119000 0 0x1000>,144 <0 0x1c11a000 0 0x1000>,145 <0 0x1c11b000 0 0x1000>,146 <0 0x1c11c000 0 0x1000>;147 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",148 "vdo_be", "adl_ds";149 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,150 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,151 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,152 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,153 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,154 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,155 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;156 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,157 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,158 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,159 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,160 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,161 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,162 <&vdosys1 CLK_VDO1_26M_SLOW>,163 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,164 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,165 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,166 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,167 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,168 <&topckgen CLK_TOP_ETHDR>;169 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",170 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",171 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",172 "ethdr_top";173 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;174 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,175 <&iommu_vpp M4U_PORT_L3_HDR_ADL>;176 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */177 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,178 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,179 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,180 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,181 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;182 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",183 "gfx_fe1_async", "vdo_be_async";184 };185 };186...187