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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Mediatek display overlay 2 layer8 9maintainers:10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>11 - Philipp Zabel <p.zabel@pengutronix.de>12 13description: |14 Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer15 for OVL.16 OVL-2L device node must be siblings to the central MMSYS_CONFIG node.17 For a description of the MMSYS_CONFIG binding, see18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml19 for details.20 21properties:22 compatible:23 oneOf:24 - enum:25 - mediatek,mt8183-disp-ovl-2l26 - mediatek,mt8192-disp-ovl-2l27 - items:28 - enum:29 - mediatek,mt8186-disp-ovl-2l30 - const: mediatek,mt8192-disp-ovl-2l31 32 reg:33 maxItems: 134 35 interrupts:36 maxItems: 137 38 power-domains:39 description: A phandle and PM domain specifier as defined by bindings of40 the power controller specified by phandle. See41 Documentation/devicetree/bindings/power/power-domain.yaml for details.42 43 clocks:44 items:45 - description: OVL-2L Clock46 47 iommus:48 description:49 This property should point to the respective IOMMU block with master port as argument,50 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.51 52 mediatek,gce-client-reg:53 description: The register of client driver can be configured by gce with54 4 arguments defined in this property, such as phandle of gce, subsys id,55 register offset and size. Each GCE subsys id is mapping to a client56 defined in the header include/dt-bindings/gce/<chip>-gce.h.57 $ref: /schemas/types.yaml#/definitions/phandle-array58 maxItems: 159 60required:61 - compatible62 - reg63 - interrupts64 - power-domains65 - clocks66 - iommus67 68additionalProperties: false69 70examples:71 - |72 #include <dt-bindings/interrupt-controller/arm-gic.h>73 #include <dt-bindings/clock/mt8183-clk.h>74 #include <dt-bindings/power/mt8183-power.h>75 #include <dt-bindings/gce/mt8183-gce.h>76 #include <dt-bindings/memory/mt8183-larb-port.h>77 78 soc {79 #address-cells = <2>;80 #size-cells = <2>;81 82 ovl_2l0: ovl@14009000 {83 compatible = "mediatek,mt8183-disp-ovl-2l";84 reg = <0 0x14009000 0 0x1000>;85 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;86 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;87 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;88 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;89 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;90 };91 };92