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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Mediatek display overlay8 9maintainers:10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>11 - Philipp Zabel <p.zabel@pengutronix.de>12 13description: |14 Mediatek display overlay, namely OVL, can do alpha blending from15 the memory.16 OVL device node must be siblings to the central MMSYS_CONFIG node.17 For a description of the MMSYS_CONFIG binding, see18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml19 for details.20 21properties:22 compatible:23 oneOf:24 - enum:25 - mediatek,mt2701-disp-ovl26 - mediatek,mt8173-disp-ovl27 - mediatek,mt8183-disp-ovl28 - mediatek,mt8192-disp-ovl29 - mediatek,mt8195-mdp3-ovl30 - items:31 - enum:32 - mediatek,mt7623-disp-ovl33 - mediatek,mt2712-disp-ovl34 - const: mediatek,mt2701-disp-ovl35 - items:36 - enum:37 - mediatek,mt6795-disp-ovl38 - const: mediatek,mt8173-disp-ovl39 - items:40 - enum:41 - mediatek,mt8188-disp-ovl42 - mediatek,mt8195-disp-ovl43 - const: mediatek,mt8183-disp-ovl44 - items:45 - enum:46 - mediatek,mt8186-disp-ovl47 - mediatek,mt8365-disp-ovl48 - const: mediatek,mt8192-disp-ovl49 50 reg:51 maxItems: 152 53 interrupts:54 maxItems: 155 56 power-domains:57 description: A phandle and PM domain specifier as defined by bindings of58 the power controller specified by phandle. See59 Documentation/devicetree/bindings/power/power-domain.yaml for details.60 61 clocks:62 items:63 - description: OVL Clock64 65 iommus:66 description:67 This property should point to the respective IOMMU block with master port as argument,68 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.69 70 mediatek,gce-client-reg:71 description: The register of client driver can be configured by gce with72 4 arguments defined in this property, such as phandle of gce, subsys id,73 register offset and size. Each GCE subsys id is mapping to a client74 defined in the header include/dt-bindings/gce/<chip>-gce.h.75 $ref: /schemas/types.yaml#/definitions/phandle-array76 maxItems: 177 78required:79 - compatible80 - reg81 - interrupts82 - power-domains83 - clocks84 - iommus85 86additionalProperties: false87 88examples:89 - |90 #include <dt-bindings/interrupt-controller/arm-gic.h>91 #include <dt-bindings/clock/mt8173-clk.h>92 #include <dt-bindings/power/mt8173-power.h>93 #include <dt-bindings/gce/mt8173-gce.h>94 #include <dt-bindings/memory/mt8173-larb-port.h>95 96 soc {97 #address-cells = <2>;98 #size-cells = <2>;99 100 ovl0: ovl@1400c000 {101 compatible = "mediatek,mt8173-disp-ovl";102 reg = <0 0x1400c000 0 0x1000>;103 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;104 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;105 clocks = <&mmsys CLK_MM_DISP_OVL0>;106 iommus = <&iommu M4U_PORT_DISP_OVL0>;107 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;108 };109 };110