329 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved3%YAML 1.24---5 6$id: http://devicetree.org/schemas/display/msm/gmu.yaml#7$schema: http://devicetree.org/meta-schemas/core.yaml#8 9title: GMU attached to certain Adreno GPUs10 11maintainers:12 - Rob Clark <robdclark@gmail.com>13 14description: |15 These bindings describe the Graphics Management Unit (GMU) that is attached16 to members of the Adreno A6xx GPU family. The GMU provides on-device power17 management and support to improve power efficiency and reduce the load on18 the CPU.19 20properties:21 compatible:22 oneOf:23 - items:24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'25 - const: qcom,adreno-gmu26 - items:27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'28 - const: qcom,adreno-gmu29 - const: qcom,adreno-gmu-wrapper30 31 reg:32 minItems: 133 maxItems: 434 35 reg-names:36 minItems: 137 maxItems: 438 39 clocks:40 minItems: 441 maxItems: 742 43 clock-names:44 minItems: 445 maxItems: 746 47 interrupts:48 items:49 - description: GMU HFI interrupt50 - description: GMU interrupt51 52 interrupt-names:53 items:54 - const: hfi55 - const: gmu56 57 power-domains:58 items:59 - description: CX power domain60 - description: GX power domain61 62 power-domain-names:63 items:64 - const: cx65 - const: gx66 67 iommus:68 maxItems: 169 70 qcom,qmp:71 $ref: /schemas/types.yaml#/definitions/phandle72 description: Reference to the AOSS side-channel message RAM73 74 operating-points-v2: true75 76 opp-table:77 type: object78 79required:80 - compatible81 - reg82 - reg-names83 - power-domains84 - power-domain-names85 86additionalProperties: false87 88allOf:89 - if:90 properties:91 compatible:92 contains:93 enum:94 - qcom,adreno-gmu-618.095 - qcom,adreno-gmu-630.296 then:97 properties:98 reg:99 items:100 - description: Core GMU registers101 - description: GMU PDC registers102 - description: GMU PDC sequence registers103 reg-names:104 items:105 - const: gmu106 - const: gmu_pdc107 - const: gmu_pdc_seq108 clocks:109 items:110 - description: GMU clock111 - description: GPU CX clock112 - description: GPU AXI clock113 - description: GPU MEMNOC clock114 clock-names:115 items:116 - const: gmu117 - const: cxo118 - const: axi119 - const: memnoc120 121 - if:122 properties:123 compatible:124 contains:125 enum:126 - qcom,adreno-gmu-635.0127 - qcom,adreno-gmu-660.1128 then:129 properties:130 reg:131 items:132 - description: Core GMU registers133 - description: Resource controller registers134 - description: GMU PDC registers135 reg-names:136 items:137 - const: gmu138 - const: rscc139 - const: gmu_pdc140 clocks:141 items:142 - description: GMU clock143 - description: GPU CX clock144 - description: GPU AXI clock145 - description: GPU MEMNOC clock146 - description: GPU AHB clock147 - description: GPU HUB CX clock148 - description: GPU SMMU vote clock149 clock-names:150 items:151 - const: gmu152 - const: cxo153 - const: axi154 - const: memnoc155 - const: ahb156 - const: hub157 - const: smmu_vote158 159 - if:160 properties:161 compatible:162 contains:163 enum:164 - qcom,adreno-gmu-640.1165 then:166 properties:167 reg:168 items:169 - description: Core GMU registers170 - description: GMU PDC registers171 - description: GMU PDC sequence registers172 reg-names:173 items:174 - const: gmu175 - const: gmu_pdc176 - const: gmu_pdc_seq177 178 - if:179 properties:180 compatible:181 contains:182 enum:183 - qcom,adreno-gmu-650.2184 then:185 properties:186 reg:187 items:188 - description: Core GMU registers189 - description: Resource controller registers190 - description: GMU PDC registers191 - description: GMU PDC sequence registers192 reg-names:193 items:194 - const: gmu195 - const: rscc196 - const: gmu_pdc197 - const: gmu_pdc_seq198 199 - if:200 properties:201 compatible:202 contains:203 enum:204 - qcom,adreno-gmu-640.1205 - qcom,adreno-gmu-650.2206 then:207 properties:208 clocks:209 items:210 - description: GPU AHB clock211 - description: GMU clock212 - description: GPU CX clock213 - description: GPU AXI clock214 - description: GPU MEMNOC clock215 clock-names:216 items:217 - const: ahb218 - const: gmu219 - const: cxo220 - const: axi221 - const: memnoc222 223 - if:224 properties:225 compatible:226 contains:227 enum:228 - qcom,adreno-gmu-730.1229 - qcom,adreno-gmu-740.1230 - qcom,adreno-gmu-750.1231 - qcom,adreno-gmu-x185.1232 then:233 properties:234 reg:235 items:236 - description: Core GMU registers237 - description: Resource controller registers238 - description: GMU PDC registers239 reg-names:240 items:241 - const: gmu242 - const: rscc243 - const: gmu_pdc244 clocks:245 items:246 - description: GPU AHB clock247 - description: GMU clock248 - description: GPU CX clock249 - description: GPU AXI clock250 - description: GPU MEMNOC clock251 - description: GMU HUB clock252 - description: GPUSS DEMET clock253 clock-names:254 items:255 - const: ahb256 - const: gmu257 - const: cxo258 - const: axi259 - const: memnoc260 - const: hub261 - const: demet262 263 required:264 - qcom,qmp265 266 - if:267 properties:268 compatible:269 contains:270 const: qcom,adreno-gmu-wrapper271 then:272 properties:273 reg:274 items:275 - description: GMU wrapper register space276 reg-names:277 items:278 - const: gmu279 else:280 required:281 - clocks282 - clock-names283 - interrupts284 - interrupt-names285 - iommus286 - operating-points-v2287 288examples:289 - |290 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>291 #include <dt-bindings/clock/qcom,gcc-sdm845.h>292 #include <dt-bindings/interrupt-controller/irq.h>293 #include <dt-bindings/interrupt-controller/arm-gic.h>294 295 gmu: gmu@506a000 {296 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";297 298 reg = <0x506a000 0x30000>,299 <0xb280000 0x10000>,300 <0xb480000 0x10000>;301 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";302 303 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,304 <&gpucc GPU_CC_CXO_CLK>,305 <&gcc GCC_DDRSS_GPU_AXI_CLK>,306 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;307 clock-names = "gmu", "cxo", "axi", "memnoc";308 309 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,310 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;311 interrupt-names = "hfi", "gmu";312 313 power-domains = <&gpucc GPU_CX_GDSC>,314 <&gpucc GPU_GX_GDSC>;315 power-domain-names = "cx", "gx";316 317 iommus = <&adreno_smmu 5>;318 operating-points-v2 = <&gmu_opp_table>;319 };320 321 gmu_wrapper: gmu@596a000 {322 compatible = "qcom,adreno-gmu-wrapper";323 reg = <0x0596a000 0x30000>;324 reg-names = "gmu";325 power-domains = <&gpucc GPU_CX_GDSC>,326 <&gpucc GPU_GX_GDSC>;327 power-domain-names = "cx", "gx";328 };329