107 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display MDSS common properties8 9maintainers:10 - Krishna Manikandan <quic_mkrishn@quicinc.com>11 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>12 - Rob Clark <robdclark@gmail.com>13 14description:15 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates16 sub-blocks like DPU display controller, DSI and DP interfaces etc.17 18# Do not select this by default, otherwise it is also selected for qcom,mdss19# devices.20select:21 false22 23properties:24 $nodename:25 pattern: "^display-subsystem@[0-9a-f]+$"26 27 reg:28 maxItems: 129 30 reg-names:31 const: mdss32 33 power-domains:34 maxItems: 135 36 clocks:37 minItems: 238 maxItems: 439 40 clock-names:41 minItems: 242 maxItems: 443 44 interrupts:45 maxItems: 146 47 interrupt-controller: true48 49 "#address-cells": true50 51 "#size-cells": true52 53 "#interrupt-cells":54 const: 155 56 iommus:57 minItems: 158 items:59 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port060 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port161 62 ranges: true63 64 # This is not a perfect description, but it's impossible to discern and match65 # the entries like we do with interconnect-names66 interconnects:67 minItems: 168 items:69 - description: Interconnect path from mdp0 (or a single mdp) port to the data bus70 - description: Interconnect path from mdp1 port to the data bus71 - description: Interconnect path from CPU to the reg bus72 73 interconnect-names:74 oneOf:75 - minItems: 176 items:77 - const: mdp0-mem78 - const: cpu-cfg79 80 - minItems: 281 items:82 - const: mdp0-mem83 - const: mdp1-mem84 - const: cpu-cfg85 86 resets:87 items:88 - description: MDSS_CORE reset89 90 memory-region:91 maxItems: 192 description:93 Phandle to a node describing a reserved framebuffer memory region.94 For example, the splash memory region set up by the bootloader.95 96required:97 - reg98 - reg-names99 - power-domains100 - clocks101 - interrupts102 - interrupt-controller103 - iommus104 - ranges105 106additionalProperties: true107