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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)8 9description:10 MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM899411 and MSM8996.12 13maintainers:14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>15 - Rob Clark <robdclark@gmail.com>16 17properties:18 compatible:19 oneOf:20 - const: qcom,mdp521 deprecated: true22 - items:23 - enum:24 - qcom,apq8084-mdp525 - qcom,msm8226-mdp526 - qcom,msm8916-mdp527 - qcom,msm8917-mdp528 - qcom,msm8937-mdp529 - qcom,msm8953-mdp530 - qcom,msm8974-mdp531 - qcom,msm8976-mdp532 - qcom,msm8994-mdp533 - qcom,msm8996-mdp534 - qcom,sdm630-mdp535 - qcom,sdm660-mdp536 - const: qcom,mdp537 38 $nodename:39 pattern: '^display-controller@[0-9a-f]+$'40 41 reg:42 maxItems: 143 44 reg-names:45 items:46 - const: mdp_phys47 48 interrupts:49 maxItems: 150 51 clocks:52 minItems: 453 maxItems: 754 55 clock-names:56 oneOf:57 - minItems: 458 items:59 - const: iface60 - const: bus61 - const: core62 - const: vsync63 - const: lut64 - const: tbu65 - const: tbu_rt66 # MSM8996 has additional iommu clock67 - items:68 - const: iface69 - const: bus70 - const: core71 - const: iommu72 - const: vsync73 74 interconnects:75 minItems: 176 items:77 - description: Interconnect path from mdp0 (or a single mdp) port to the data bus78 - description: Interconnect path from mdp1 port to the data bus79 - description: Interconnect path from rotator port to the data bus80 81 interconnect-names:82 minItems: 183 items:84 - const: mdp0-mem85 - const: mdp1-mem86 - const: rotator-mem87 88 iommus:89 items:90 - description: apps SMMU with the Stream-ID mask for Hard-Fail port091 92 power-domains:93 maxItems: 194 95 operating-points-v2: true96 opp-table:97 type: object98 99 ports:100 $ref: /schemas/graph.yaml#/properties/ports101 description: >102 Contains the list of output ports from DPU device. These ports103 connect to interfaces that are external to the DPU hardware,104 such as DSI, DP etc. MDP5 devices support up to 4 ports:105 one or two DSI ports, HDMI and eDP.106 107 patternProperties:108 "^port@[0-3]+$":109 $ref: /schemas/graph.yaml#/properties/port110 111 # at least one port is required112 required:113 - port@0114 115required:116 - compatible117 - reg118 - reg-names119 - clocks120 - clock-names121 - ports122 123additionalProperties: false124 125examples:126 - |127 #include <dt-bindings/clock/qcom,gcc-msm8916.h>128 #include <dt-bindings/interrupt-controller/arm-gic.h>129 display-controller@1a01000 {130 compatible = "qcom,mdp5";131 reg = <0x1a01000 0x90000>;132 reg-names = "mdp_phys";133 134 interrupt-parent = <&mdss>;135 interrupts = <0>;136 137 clocks = <&gcc GCC_MDSS_AHB_CLK>,138 <&gcc GCC_MDSS_AXI_CLK>,139 <&gcc GCC_MDSS_MDP_CLK>,140 <&gcc GCC_MDSS_VSYNC_CLK>;141 clock-names = "iface",142 "bus",143 "core",144 "vsync";145 146 ports {147 #address-cells = <1>;148 #size-cells = <0>;149 150 port@0 {151 reg = <0>;152 endpoint {153 remote-endpoint = <&dsi0_in>;154 };155 };156 };157 };158...159