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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Mobile Display SubSystem (MDSS)8 9maintainers:10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>11  - Rob Clark <robdclark@gmail.com>12 13description:14  This is the bindings documentation for the Mobile Display Subsystem(MDSS) that15  encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.16 17properties:18  $nodename:19    pattern: "^display-subsystem@[0-9a-f]+$"20 21  compatible:22    enum:23      - qcom,mdss24 25  reg:26    minItems: 227    maxItems: 328 29  reg-names:30    minItems: 231    items:32      - const: mdss_phys33      - const: vbif_phys34      - const: vbif_nrt_phys35 36  interrupts:37    maxItems: 138 39  interrupt-controller: true40 41  "#interrupt-cells":42    const: 143 44  power-domains:45    maxItems: 146    description: |47      The MDSS power domain provided by GCC48 49  clocks:50    oneOf:51      - minItems: 352        items:53          - description: Display abh clock54          - description: Display axi clock55          - description: Display vsync clock56          - description: Display core clock57      - minItems: 158        items:59          - description: Display abh clock60          - description: Display core clock61 62  clock-names:63    oneOf:64      - minItems: 365        items:66          - const: iface67          - const: bus68          - const: vsync69          - const: core70      - minItems: 171        items:72          - const: iface73          - const: core74 75  "#address-cells":76    const: 177 78  "#size-cells":79    const: 180 81  ranges: true82 83  resets:84    items:85      - description: MDSS_CORE reset86 87required:88  - compatible89  - reg90  - reg-names91  - interrupts92  - interrupt-controller93  - "#interrupt-cells"94  - power-domains95  - clocks96  - clock-names97  - "#address-cells"98  - "#size-cells"99  - ranges100 101patternProperties:102  "^display-controller@[1-9a-f][0-9a-f]*$":103    type: object104    additionalProperties: true105    properties:106      compatible:107        contains:108          const: qcom,mdp5109 110  "^dsi@[1-9a-f][0-9a-f]*$":111    type: object112    additionalProperties: true113    properties:114      compatible:115        contains:116          const: qcom,mdss-dsi-ctrl117 118  "^phy@[1-9a-f][0-9a-f]*$":119    type: object120    additionalProperties: true121    properties:122      compatible:123        enum:124          - qcom,dsi-phy-14nm125          - qcom,dsi-phy-14nm-660126          - qcom,dsi-phy-14nm-8953127          - qcom,dsi-phy-20nm128          - qcom,dsi-phy-28nm-8226129          - qcom,dsi-phy-28nm-8937130          - qcom,dsi-phy-28nm-hpm131          - qcom,dsi-phy-28nm-hpm-fam-b132          - qcom,dsi-phy-28nm-lp133          - qcom,hdmi-phy-8084134          - qcom,hdmi-phy-8660135          - qcom,hdmi-phy-8960136          - qcom,hdmi-phy-8974137          - qcom,hdmi-phy-8996138 139  "^hdmi-tx@[1-9a-f][0-9a-f]*$":140    type: object141    additionalProperties: true142    properties:143      compatible:144        enum:145          - qcom,hdmi-tx-8084146          - qcom,hdmi-tx-8660147          - qcom,hdmi-tx-8960148          - qcom,hdmi-tx-8974149          - qcom,hdmi-tx-8994150          - qcom,hdmi-tx-8996151 152additionalProperties: false153 154examples:155  - |156    #include <dt-bindings/clock/qcom,gcc-msm8916.h>157    #include <dt-bindings/interrupt-controller/arm-gic.h>158    display-subsystem@1a00000 {159        compatible = "qcom,mdss";160        reg = <0x1a00000 0x1000>,161              <0x1ac8000 0x3000>;162        reg-names = "mdss_phys", "vbif_phys";163 164        power-domains = <&gcc MDSS_GDSC>;165 166        clocks = <&gcc GCC_MDSS_AHB_CLK>,167                 <&gcc GCC_MDSS_AXI_CLK>,168                 <&gcc GCC_MDSS_VSYNC_CLK>;169        clock-names = "iface",170                      "bus",171                      "vsync";172 173        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;174 175        interrupt-controller;176        #interrupt-cells = <1>;177 178        #address-cells = <1>;179        #size-cells = <1>;180        ranges;181 182        display-controller@1a01000 {183            compatible = "qcom,msm8916-mdp5", "qcom,mdp5";184            reg = <0x01a01000 0x89000>;185            reg-names = "mdp_phys";186 187            interrupt-parent = <&mdss>;188            interrupts = <0>;189 190            clocks = <&gcc GCC_MDSS_AHB_CLK>,191                     <&gcc GCC_MDSS_AXI_CLK>,192                     <&gcc GCC_MDSS_MDP_CLK>,193                     <&gcc GCC_MDSS_VSYNC_CLK>;194            clock-names = "iface",195                      "bus",196                      "core",197                      "vsync";198 199            iommus = <&apps_iommu 4>;200 201            ports {202                #address-cells = <1>;203                #size-cells = <0>;204 205                port@0 {206                    reg = <0>;207                    mdp5_intf1_out: endpoint {208                        remote-endpoint = <&dsi0_in>;209                    };210                };211            };212        };213    };214...215