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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display DPU on QCM22908 9maintainers:10 - Loic Poulain <loic.poulain@linaro.org>11 12$ref: /schemas/display/msm/dpu-common.yaml#13 14properties:15 compatible:16 const: qcom,qcm2290-dpu17 18 reg:19 items:20 - description: Address offset and size for mdp register set21 - description: Address offset and size for vbif register set22 23 reg-names:24 items:25 - const: mdp26 - const: vbif27 28 clocks:29 items:30 - description: Display AXI clock from gcc31 - description: Display AHB clock from dispcc32 - description: Display core clock from dispcc33 - description: Display lut clock from dispcc34 - description: Display vsync clock from dispcc35 36 clock-names:37 items:38 - const: bus39 - const: iface40 - const: core41 - const: lut42 - const: vsync43 44required:45 - compatible46 - reg47 - reg-names48 - clocks49 - clock-names50 51unevaluatedProperties: false52 53examples:54 - |55 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>56 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>57 #include <dt-bindings/power/qcom-rpmpd.h>58 59 display-controller@5e01000 {60 compatible = "qcom,qcm2290-dpu";61 reg = <0x05e01000 0x8f000>,62 <0x05eb0000 0x2008>;63 reg-names = "mdp", "vbif";64 65 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,66 <&dispcc DISP_CC_MDSS_AHB_CLK>,67 <&dispcc DISP_CC_MDSS_MDP_CLK>,68 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,69 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;70 clock-names = "bus", "iface", "core", "lut", "vsync";71 72 operating-points-v2 = <&mdp_opp_table>;73 power-domains = <&rpmpd QCM2290_VDDCX>;74 75 interrupt-parent = <&mdss>;76 interrupts = <0>;77 78 ports {79 #address-cells = <1>;80 #size-cells = <0>;81 82 port@0 {83 reg = <0>;84 endpoint {85 remote-endpoint = <&dsi0_in>;86 };87 };88 };89 };90...91