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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SC8280XP Mobile Display Subsystem8 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 12description:13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates14 sub-blocks like DPU display controller, DSI and DP interfaces etc.15 16$ref: /schemas/display/msm/mdss-common.yaml#17 18properties:19 compatible:20 const: qcom,sc8280xp-mdss21 22 clocks:23 items:24 - description: Display AHB clock from gcc25 - description: Display AHB clock from dispcc26 - description: Display core clock27 28 clock-names:29 items:30 - const: iface31 - const: ahb32 - const: core33 34patternProperties:35 "^display-controller@[0-9a-f]+$":36 type: object37 additionalProperties: true38 39 properties:40 compatible:41 const: qcom,sc8280xp-dpu42 43 "^displayport-controller@[0-9a-f]+$":44 type: object45 additionalProperties: true46 47 properties:48 compatible:49 enum:50 - qcom,sc8280xp-dp51 - qcom,sc8280xp-edp52 53unevaluatedProperties: false54 55examples:56 - |57 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>58 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>59 #include <dt-bindings/interrupt-controller/arm-gic.h>60 #include <dt-bindings/interconnect/qcom,sc8280xp.h>61 #include <dt-bindings/power/qcom-rpmpd.h>62 63 display-subsystem@ae00000 {64 compatible = "qcom,sc8280xp-mdss";65 reg = <0x0ae00000 0x1000>;66 reg-names = "mdss";67 68 power-domains = <&dispcc0 MDSS_GDSC>;69 70 clocks = <&gcc GCC_DISP_AHB_CLK>,71 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,72 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;73 clock-names = "iface",74 "ahb",75 "core";76 77 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;78 79 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;80 interrupt-controller;81 #interrupt-cells = <1>;82 83 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,84 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;85 interconnect-names = "mdp0-mem", "mdp1-mem";86 87 iommus = <&apps_smmu 0x1000 0x402>;88 89 #address-cells = <1>;90 #size-cells = <1>;91 ranges;92 93 display-controller@ae01000 {94 compatible = "qcom,sc8280xp-dpu";95 reg = <0x0ae01000 0x8f000>,96 <0x0aeb0000 0x2008>;97 reg-names = "mdp", "vbif";98 99 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,100 <&gcc GCC_DISP_SF_AXI_CLK>,101 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,102 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,103 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,104 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;105 clock-names = "bus",106 "nrt_bus",107 "iface",108 "lut",109 "core",110 "vsync";111 112 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;113 assigned-clock-rates = <19200000>;114 115 operating-points-v2 = <&mdss0_mdp_opp_table>;116 power-domains = <&rpmhpd SC8280XP_MMCX>;117 118 interrupt-parent = <&mdss0>;119 interrupts = <0>;120 121 ports {122 #address-cells = <1>;123 #size-cells = <0>;124 125 port@0 {126 reg = <0>;127 endpoint {128 remote-endpoint = <&mdss0_dp0_in>;129 };130 };131 132 port@4 {133 reg = <4>;134 endpoint {135 remote-endpoint = <&mdss0_dp1_in>;136 };137 };138 139 port@5 {140 reg = <5>;141 endpoint {142 remote-endpoint = <&mdss0_dp3_in>;143 };144 };145 146 port@6 {147 reg = <6>;148 endpoint {149 remote-endpoint = <&mdss0_dp2_in>;150 };151 };152 };153 };154 };155...156