94 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display DPU on SM61158 9maintainers:10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>11 12$ref: /schemas/display/msm/dpu-common.yaml#13 14properties:15 compatible:16 const: qcom,sm6115-dpu17 18 reg:19 items:20 - description: MDP register set21 - description: VBIF register set22 23 reg-names:24 items:25 - const: mdp26 - const: vbif27 28 clocks:29 items:30 - description: Display AXI31 - description: Display AHB32 - description: Display core33 - description: Display lut34 - description: Display rotator35 - description: Display vsync36 37 clock-names:38 items:39 - const: bus40 - const: iface41 - const: core42 - const: lut43 - const: rot44 - const: vsync45 46required:47 - compatible48 - reg49 - reg-names50 - clocks51 - clock-names52 53unevaluatedProperties: false54 55examples:56 - |57 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>58 #include <dt-bindings/clock/qcom,gcc-sm6115.h>59 #include <dt-bindings/power/qcom-rpmpd.h>60 61 display-controller@5e01000 {62 compatible = "qcom,sm6115-dpu";63 reg = <0x05e01000 0x8f000>,64 <0x05eb0000 0x2008>;65 reg-names = "mdp", "vbif";66 67 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,68 <&dispcc DISP_CC_MDSS_AHB_CLK>,69 <&dispcc DISP_CC_MDSS_MDP_CLK>,70 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,71 <&dispcc DISP_CC_MDSS_ROT_CLK>,72 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;73 clock-names = "bus", "iface", "core", "lut", "rot", "vsync";74 75 operating-points-v2 = <&mdp_opp_table>;76 power-domains = <&rpmpd SM6115_VDDCX>;77 78 interrupt-parent = <&mdss>;79 interrupts = <0>;80 81 ports {82 #address-cells = <1>;83 #size-cells = <0>;84 85 port@0 {86 reg = <0>;87 endpoint {88 remote-endpoint = <&dsi0_in>;89 };90 };91 };92 };93...94