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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SM6350 Display MDSS8 9maintainers:10 - Krishna Manikandan <quic_mkrishn@quicinc.com>11 12description:13 SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks14 like DPU display controller, DSI and DP interfaces etc.15 16$ref: /schemas/display/msm/mdss-common.yaml#17 18properties:19 compatible:20 const: qcom,sm6350-mdss21 22 clocks:23 items:24 - description: Display AHB clock from gcc25 - description: Display AXI clock from gcc26 - description: Display core clock27 28 clock-names:29 items:30 - const: iface31 - const: bus32 - const: core33 34 iommus:35 maxItems: 136 37 interconnects:38 items:39 - description: Interconnect path from mdp0 port to the data bus40 - description: Interconnect path from CPU to the reg bus41 42 interconnect-names:43 items:44 - const: mdp0-mem45 - const: cpu-cfg46 47patternProperties:48 "^display-controller@[0-9a-f]+$":49 type: object50 additionalProperties: true51 52 properties:53 compatible:54 const: qcom,sm6350-dpu55 56 "^displayport-controller@[0-9a-f]+$":57 type: object58 additionalProperties: true59 60 properties:61 compatible:62 contains:63 const: qcom,sm6350-dp64 65 "^dsi@[0-9a-f]+$":66 type: object67 additionalProperties: true68 69 properties:70 compatible:71 items:72 - const: qcom,sm6350-dsi-ctrl73 - const: qcom,mdss-dsi-ctrl74 75 "^phy@[0-9a-f]+$":76 type: object77 additionalProperties: true78 79 properties:80 compatible:81 const: qcom,dsi-phy-10nm82 83unevaluatedProperties: false84 85examples:86 - |87 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>88 #include <dt-bindings/clock/qcom,gcc-sm6350.h>89 #include <dt-bindings/clock/qcom,rpmh.h>90 #include <dt-bindings/interrupt-controller/arm-gic.h>91 #include <dt-bindings/power/qcom-rpmpd.h>92 93 display-subsystem@ae00000 {94 compatible = "qcom,sm6350-mdss";95 reg = <0x0ae00000 0x1000>;96 reg-names = "mdss";97 98 power-domains = <&dispcc MDSS_GDSC>;99 100 clocks = <&gcc GCC_DISP_AHB_CLK>,101 <&gcc GCC_DISP_AXI_CLK>,102 <&dispcc DISP_CC_MDSS_MDP_CLK>;103 clock-names = "iface", "bus", "core";104 105 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;106 interrupt-controller;107 #interrupt-cells = <1>;108 109 iommus = <&apps_smmu 0x800 0x2>;110 #address-cells = <1>;111 #size-cells = <1>;112 ranges;113 114 display-controller@ae01000 {115 compatible = "qcom,sm6350-dpu";116 reg = <0x0ae01000 0x8f000>,117 <0x0aeb0000 0x2008>;118 reg-names = "mdp", "vbif";119 120 clocks = <&gcc GCC_DISP_AXI_CLK>,121 <&dispcc DISP_CC_MDSS_AHB_CLK>,122 <&dispcc DISP_CC_MDSS_ROT_CLK>,123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,124 <&dispcc DISP_CC_MDSS_MDP_CLK>,125 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;126 clock-names = "bus", "iface", "rot", "lut", "core",127 "vsync";128 129 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,131 <&dispcc DISP_CC_MDSS_ROT_CLK>,132 <&dispcc DISP_CC_MDSS_AHB_CLK>;133 assigned-clock-rates = <300000000>,134 <19200000>,135 <19200000>,136 <19200000>;137 138 interrupt-parent = <&mdss>;139 interrupts = <0>;140 operating-points-v2 = <&mdp_opp_table>;141 power-domains = <&rpmhpd SM6350_CX>;142 143 ports {144 #address-cells = <1>;145 #size-cells = <0>;146 147 port@0 {148 reg = <0>;149 dpu_intf1_out: endpoint {150 remote-endpoint = <&dsi0_in>;151 };152 };153 };154 };155 156 dsi@ae94000 {157 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";158 reg = <0x0ae94000 0x400>;159 reg-names = "dsi_ctrl";160 161 interrupt-parent = <&mdss>;162 interrupts = <4>;163 164 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,165 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,166 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,167 <&dispcc DISP_CC_MDSS_ESC0_CLK>,168 <&dispcc DISP_CC_MDSS_AHB_CLK>,169 <&gcc GCC_DISP_AXI_CLK>;170 clock-names = "byte",171 "byte_intf",172 "pixel",173 "core",174 "iface",175 "bus";176 177 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,178 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;179 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;180 181 operating-points-v2 = <&dsi_opp_table>;182 power-domains = <&rpmhpd SM6350_MX>;183 184 phys = <&dsi0_phy>;185 phy-names = "dsi";186 187 #address-cells = <1>;188 #size-cells = <0>;189 190 ports {191 #address-cells = <1>;192 #size-cells = <0>;193 194 port@0 {195 reg = <0>;196 dsi0_in: endpoint {197 remote-endpoint = <&dpu_intf1_out>;198 };199 };200 201 port@1 {202 reg = <1>;203 dsi0_out: endpoint {204 };205 };206 };207 };208 209 dsi0_phy: phy@ae94400 {210 compatible = "qcom,dsi-phy-10nm";211 reg = <0x0ae94400 0x200>,212 <0x0ae94600 0x280>,213 <0x0ae94a00 0x1e0>;214 reg-names = "dsi_phy",215 "dsi_phy_lane",216 "dsi_pll";217 218 #clock-cells = <1>;219 #phy-cells = <0>;220 221 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;222 clock-names = "iface", "ref";223 };224 };225...226