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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-dpu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SM8150 Display DPU8 9maintainers:10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>11 12$ref: /schemas/display/msm/dpu-common.yaml#13 14properties:15 compatible:16 const: qcom,sm8150-dpu17 18 reg:19 items:20 - description: Address offset and size for mdp register set21 - description: Address offset and size for vbif register set22 23 reg-names:24 items:25 - const: mdp26 - const: vbif27 28 clocks:29 items:30 - description: Display ahb clock31 - description: Display hf axi clock32 - description: Display core clock33 - description: Display vsync clock34 35 clock-names:36 items:37 - const: iface38 - const: bus39 - const: core40 - const: vsync41 42unevaluatedProperties: false43 44examples:45 - |46 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>47 #include <dt-bindings/clock/qcom,gcc-sm8150.h>48 #include <dt-bindings/interrupt-controller/arm-gic.h>49 #include <dt-bindings/interconnect/qcom,sm8150.h>50 #include <dt-bindings/power/qcom-rpmpd.h>51 52 display-controller@ae01000 {53 compatible = "qcom,sm8150-dpu";54 reg = <0x0ae01000 0x8f000>,55 <0x0aeb0000 0x2008>;56 reg-names = "mdp", "vbif";57 58 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,59 <&gcc GCC_DISP_HF_AXI_CLK>,60 <&dispcc DISP_CC_MDSS_MDP_CLK>,61 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;62 clock-names = "iface", "bus", "core", "vsync";63 64 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;65 assigned-clock-rates = <19200000>;66 67 operating-points-v2 = <&mdp_opp_table>;68 power-domains = <&rpmhpd SM8150_MMCX>;69 70 interrupt-parent = <&mdss>;71 interrupts = <0>;72 73 ports {74 #address-cells = <1>;75 #size-cells = <0>;76 77 port@0 {78 reg = <0>;79 endpoint {80 remote-endpoint = <&dsi0_in>;81 };82 };83 84 port@1 {85 reg = <1>;86 endpoint {87 remote-endpoint = <&dsi1_in>;88 };89 };90 };91 };92...93