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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SM8550 Display MDSS8 9maintainers:10 - Neil Armstrong <neil.armstrong@linaro.org>11 12description:13 SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like14 DPU display controller, DSI and DP interfaces etc.15 16$ref: /schemas/display/msm/mdss-common.yaml#17 18properties:19 compatible:20 const: qcom,sm8550-mdss21 22 clocks:23 items:24 - description: Display MDSS AHB25 - description: Display AHB26 - description: Display hf AXI27 - description: Display core28 29 iommus:30 maxItems: 131 32 interconnects:33 maxItems: 234 35 interconnect-names:36 maxItems: 237 38patternProperties:39 "^display-controller@[0-9a-f]+$":40 type: object41 additionalProperties: true42 43 properties:44 compatible:45 const: qcom,sm8550-dpu46 47 "^displayport-controller@[0-9a-f]+$":48 type: object49 additionalProperties: true50 51 properties:52 compatible:53 items:54 - const: qcom,sm8550-dp55 - const: qcom,sm8350-dp56 57 "^dsi@[0-9a-f]+$":58 type: object59 additionalProperties: true60 61 properties:62 compatible:63 items:64 - const: qcom,sm8550-dsi-ctrl65 - const: qcom,mdss-dsi-ctrl66 67 "^phy@[0-9a-f]+$":68 type: object69 additionalProperties: true70 71 properties:72 compatible:73 const: qcom,sm8550-dsi-phy-4nm74 75required:76 - compatible77 78unevaluatedProperties: false79 80examples:81 - |82 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>83 #include <dt-bindings/clock/qcom,sm8550-gcc.h>84 #include <dt-bindings/clock/qcom,rpmh.h>85 #include <dt-bindings/interrupt-controller/arm-gic.h>86 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>87 #include <dt-bindings/power/qcom,rpmhpd.h>88 89 display-subsystem@ae00000 {90 compatible = "qcom,sm8550-mdss";91 reg = <0x0ae00000 0x1000>;92 reg-names = "mdss";93 94 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,95 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;96 interconnect-names = "mdp0-mem", "mdp1-mem";97 98 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;99 100 power-domains = <&dispcc MDSS_GDSC>;101 102 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,103 <&gcc GCC_DISP_AHB_CLK>,104 <&gcc GCC_DISP_HF_AXI_CLK>,105 <&dispcc DISP_CC_MDSS_MDP_CLK>;106 clock-names = "iface", "bus", "nrt_bus", "core";107 108 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;109 interrupt-controller;110 #interrupt-cells = <1>;111 112 iommus = <&apps_smmu 0x1c00 0x2>;113 114 #address-cells = <1>;115 #size-cells = <1>;116 ranges;117 118 display-controller@ae01000 {119 compatible = "qcom,sm8550-dpu";120 reg = <0x0ae01000 0x8f000>,121 <0x0aeb0000 0x2008>;122 reg-names = "mdp", "vbif";123 124 clocks = <&gcc GCC_DISP_AHB_CLK>,125 <&gcc GCC_DISP_HF_AXI_CLK>,126 <&dispcc DISP_CC_MDSS_AHB_CLK>,127 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,128 <&dispcc DISP_CC_MDSS_MDP_CLK>,129 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;130 clock-names = "bus",131 "nrt_bus",132 "iface",133 "lut",134 "core",135 "vsync";136 137 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;138 assigned-clock-rates = <19200000>;139 140 operating-points-v2 = <&mdp_opp_table>;141 power-domains = <&rpmhpd RPMHPD_MMCX>;142 143 interrupt-parent = <&mdss>;144 interrupts = <0>;145 146 ports {147 #address-cells = <1>;148 #size-cells = <0>;149 150 port@0 {151 reg = <0>;152 dpu_intf1_out: endpoint {153 remote-endpoint = <&dsi0_in>;154 };155 };156 157 port@1 {158 reg = <1>;159 dpu_intf2_out: endpoint {160 remote-endpoint = <&dsi1_in>;161 };162 };163 };164 165 mdp_opp_table: opp-table {166 compatible = "operating-points-v2";167 168 opp-200000000 {169 opp-hz = /bits/ 64 <200000000>;170 required-opps = <&rpmhpd_opp_low_svs>;171 };172 173 opp-325000000 {174 opp-hz = /bits/ 64 <325000000>;175 required-opps = <&rpmhpd_opp_svs>;176 };177 178 opp-375000000 {179 opp-hz = /bits/ 64 <375000000>;180 required-opps = <&rpmhpd_opp_svs_l1>;181 };182 183 opp-514000000 {184 opp-hz = /bits/ 64 <514000000>;185 required-opps = <&rpmhpd_opp_nom>;186 };187 };188 };189 190 dsi@ae94000 {191 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";192 reg = <0x0ae94000 0x400>;193 reg-names = "dsi_ctrl";194 195 interrupt-parent = <&mdss>;196 interrupts = <4>;197 198 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,199 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,200 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,201 <&dispcc DISP_CC_MDSS_ESC0_CLK>,202 <&dispcc DISP_CC_MDSS_AHB_CLK>,203 <&gcc GCC_DISP_HF_AXI_CLK>;204 clock-names = "byte",205 "byte_intf",206 "pixel",207 "core",208 "iface",209 "bus";210 211 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,212 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;213 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;214 215 operating-points-v2 = <&dsi_opp_table>;216 power-domains = <&rpmhpd RPMHPD_MMCX>;217 218 phys = <&dsi0_phy>;219 phy-names = "dsi";220 221 #address-cells = <1>;222 #size-cells = <0>;223 224 ports {225 #address-cells = <1>;226 #size-cells = <0>;227 228 port@0 {229 reg = <0>;230 dsi0_in: endpoint {231 remote-endpoint = <&dpu_intf1_out>;232 };233 };234 235 port@1 {236 reg = <1>;237 dsi0_out: endpoint {238 };239 };240 };241 242 dsi_opp_table: opp-table {243 compatible = "operating-points-v2";244 245 opp-187500000 {246 opp-hz = /bits/ 64 <187500000>;247 required-opps = <&rpmhpd_opp_low_svs>;248 };249 250 opp-300000000 {251 opp-hz = /bits/ 64 <300000000>;252 required-opps = <&rpmhpd_opp_svs>;253 };254 255 opp-358000000 {256 opp-hz = /bits/ 64 <358000000>;257 required-opps = <&rpmhpd_opp_svs_l1>;258 };259 };260 };261 262 dsi0_phy: phy@ae94400 {263 compatible = "qcom,sm8550-dsi-phy-4nm";264 reg = <0x0ae95000 0x200>,265 <0x0ae95200 0x280>,266 <0x0ae95500 0x400>;267 reg-names = "dsi_phy",268 "dsi_phy_lane",269 "dsi_pll";270 271 #clock-cells = <1>;272 #phy-cells = <0>;273 274 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,275 <&rpmhcc RPMH_CXO_CLK>;276 clock-names = "iface", "ref";277 };278 279 dsi@ae96000 {280 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";281 reg = <0x0ae96000 0x400>;282 reg-names = "dsi_ctrl";283 284 interrupt-parent = <&mdss>;285 interrupts = <5>;286 287 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,288 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,289 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,290 <&dispcc DISP_CC_MDSS_ESC1_CLK>,291 <&dispcc DISP_CC_MDSS_AHB_CLK>,292 <&gcc GCC_DISP_HF_AXI_CLK>;293 clock-names = "byte",294 "byte_intf",295 "pixel",296 "core",297 "iface",298 "bus";299 300 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,301 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;302 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;303 304 operating-points-v2 = <&dsi_opp_table>;305 power-domains = <&rpmhpd RPMHPD_MMCX>;306 307 phys = <&dsi1_phy>;308 phy-names = "dsi";309 310 #address-cells = <1>;311 #size-cells = <0>;312 313 ports {314 #address-cells = <1>;315 #size-cells = <0>;316 317 port@0 {318 reg = <0>;319 dsi1_in: endpoint {320 remote-endpoint = <&dpu_intf2_out>;321 };322 };323 324 port@1 {325 reg = <1>;326 dsi1_out: endpoint {327 };328 };329 };330 };331 332 dsi1_phy: phy@ae96400 {333 compatible = "qcom,sm8550-dsi-phy-4nm";334 reg = <0x0ae97000 0x200>,335 <0x0ae97200 0x280>,336 <0x0ae97500 0x400>;337 reg-names = "dsi_phy",338 "dsi_phy_lane",339 "dsi_pll";340 341 #clock-cells = <1>;342 #phy-cells = <0>;343 344 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,345 <&rpmhcc RPMH_CXO_CLK>;346 clock-names = "iface", "ref";347 };348 };349...350