104 lines · yaml
1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip specific extensions to the Analogix Display Port8 9maintainers:10 - Sandy Huang <hjc@rock-chips.com>11 - Heiko Stuebner <heiko@sntech.de>12 13properties:14 compatible:15 enum:16 - rockchip,rk3288-dp17 - rockchip,rk3399-edp18 19 clocks:20 minItems: 221 maxItems: 322 23 clock-names:24 minItems: 225 items:26 - const: dp27 - const: pclk28 - const: grf29 30 power-domains:31 maxItems: 132 33 resets:34 maxItems: 135 36 reset-names:37 const: dp38 39 rockchip,grf:40 $ref: /schemas/types.yaml#/definitions/phandle41 description:42 This SoC makes use of GRF regs.43 44required:45 - compatible46 - clocks47 - clock-names48 - resets49 - reset-names50 - rockchip,grf51 52allOf:53 - $ref: /schemas/display/bridge/analogix,dp.yaml#54 55unevaluatedProperties: false56 57examples:58 - |59 #include <dt-bindings/clock/rk3288-cru.h>60 #include <dt-bindings/interrupt-controller/arm-gic.h>61 #include <dt-bindings/interrupt-controller/irq.h>62 dp@ff970000 {63 compatible = "rockchip,rk3288-dp";64 reg = <0xff970000 0x4000>;65 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;66 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;67 clock-names = "dp", "pclk";68 phys = <&dp_phy>;69 phy-names = "dp";70 resets = <&cru 111>;71 reset-names = "dp";72 rockchip,grf = <&grf>;73 pinctrl-0 = <&edp_hpd>;74 pinctrl-names = "default";75 76 ports {77 #address-cells = <1>;78 #size-cells = <0>;79 80 edp_in: port@0 {81 reg = <0>;82 #address-cells = <1>;83 #size-cells = <0>;84 85 edp_in_vopb: endpoint@0 {86 reg = <0>;87 remote-endpoint = <&vopb_out_edp>;88 };89 edp_in_vopl: endpoint@1 {90 reg = <1>;91 remote-endpoint = <&vopl_out_edp>;92 };93 };94 95 edp_out: port@1 {96 reg = <1>;97 98 edp_out_panel: endpoint {99 remote-endpoint = <&panel_in_edp>;100 };101 };102 };103 };104