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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip DWC HDMI TX Encoder8 9maintainers:10 - Mark Yao <markyao0591@gmail.com>11 12description: |13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP14 with a companion PHY IP.15 16allOf:17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#18 - $ref: /schemas/sound/dai-common.yaml#19 20properties:21 compatible:22 enum:23 - rockchip,rk3228-dw-hdmi24 - rockchip,rk3288-dw-hdmi25 - rockchip,rk3328-dw-hdmi26 - rockchip,rk3399-dw-hdmi27 - rockchip,rk3568-dw-hdmi28 29 reg-io-width:30 const: 431 32 avdd-0v9-supply:33 description:34 A 0.9V supply that powers up the SoC internal circuitry. The actual pin name35 varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes36 HDMI_AVDD_1V0.37 38 avdd-1v8-supply:39 description:40 A 1.8V supply that powers up the SoC internal circuitry. The pin name on the41 SoC usually is HDMI_TX_AVDD_1V8.42 43 clocks:44 minItems: 245 items:46 - {}47 - {}48 # The next three clocks are all optional, but shall be specified in this49 # order when present.50 - description: The HDMI CEC controller main clock51 - description: Power for GRF IO52 - description: External clock for some HDMI PHY (old clock name, deprecated)53 - description: External clock for some HDMI PHY (new name)54 55 clock-names:56 minItems: 257 items:58 - {}59 - {}60 - enum:61 - cec62 - grf63 - vpll64 - ref65 - enum:66 - grf67 - vpll68 - ref69 - enum:70 - vpll71 - ref72 73 phys:74 maxItems: 175 description: The HDMI PHY76 77 phy-names:78 const: hdmi79 80 pinctrl-names:81 description:82 The unwedge pinctrl entry shall drive the DDC SDA line low. This is83 intended to work around a hardware errata that can cause the DDC I2C84 bus to be wedged.85 minItems: 186 items:87 - const: default88 - const: unwedge89 90 power-domains:91 maxItems: 192 93 ports:94 $ref: /schemas/graph.yaml#/properties/ports95 96 properties:97 port@0:98 $ref: /schemas/graph.yaml#/properties/port99 description: Input of the DWC HDMI TX100 properties:101 endpoint:102 description: Connection to the VOP103 endpoint@0:104 description: Connection to the VOPB105 endpoint@1:106 description: Connection to the VOPL107 port@1:108 $ref: /schemas/graph.yaml#/properties/port109 description: Output of the DWC HDMI TX110 111 required:112 - port@0113 - port@1114 115 rockchip,grf:116 $ref: /schemas/types.yaml#/definitions/phandle117 description:118 phandle to the GRF to mux vopl/vopb.119 120 "#sound-dai-cells":121 const: 0122 123required:124 - compatible125 - reg126 - reg-io-width127 - clocks128 - clock-names129 - interrupts130 - ports131 - rockchip,grf132 133unevaluatedProperties: false134 135examples:136 - |137 #include <dt-bindings/clock/rk3288-cru.h>138 #include <dt-bindings/interrupt-controller/arm-gic.h>139 #include <dt-bindings/interrupt-controller/irq.h>140 #include <dt-bindings/power/rk3288-power.h>141 142 hdmi: hdmi@ff980000 {143 compatible = "rockchip,rk3288-dw-hdmi";144 reg = <0xff980000 0x20000>;145 reg-io-width = <4>;146 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;147 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;148 clock-names = "iahb", "isfr";149 ddc-i2c-bus = <&i2c5>;150 power-domains = <&power RK3288_PD_VIO>;151 rockchip,grf = <&grf>;152 #sound-dai-cells = <0>;153 154 ports {155 #address-cells = <1>;156 #size-cells = <0>;157 158 port@0 {159 reg = <0>;160 #address-cells = <1>;161 #size-cells = <0>;162 163 hdmi_in_vopb: endpoint@0 {164 reg = <0>;165 remote-endpoint = <&vopb_out_hdmi>;166 };167 168 hdmi_in_vopl: endpoint@1 {169 reg = <1>;170 remote-endpoint = <&vopl_out_hdmi>;171 };172 };173 174 port@1 {175 reg = <1>;176 177 hdmi_out_con: endpoint {178 remote-endpoint = <&hdmi_con_in>;179 };180 };181 };182 };183 184...185