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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip SoC display controller (VOP)8 9description:10 VOP (Video Output Processor) is the display controller for the Rockchip11 series of SoCs which transfers the image data from a video memory12 buffer to an external LCD interface.13 14maintainers:15 - Sandy Huang <hjc@rock-chips.com>16 - Heiko Stuebner <heiko@sntech.de>17 18properties:19 compatible:20 enum:21 - rockchip,px30-vop-big22 - rockchip,px30-vop-lit23 - rockchip,rk3036-vop24 - rockchip,rk3066-vop25 - rockchip,rk3126-vop26 - rockchip,rk3188-vop27 - rockchip,rk3228-vop28 - rockchip,rk3288-vop29 - rockchip,rk3328-vop30 - rockchip,rk3366-vop31 - rockchip,rk3368-vop32 - rockchip,rk3399-vop-big33 - rockchip,rk3399-vop-lit34 - rockchip,rv1126-vop35 36 reg:37 minItems: 138 items:39 - description:40 Must contain one entry corresponding to the base address and length41 of the register space.42 - description:43 Can optionally contain a second entry corresponding to44 the CRTC gamma LUT address.45 46 interrupts:47 maxItems: 148 description:49 The VOP interrupt is shared by several interrupt sources, such as50 frame start (VSYNC), line flag and other status interrupts.51 52 clocks:53 items:54 - description: Clock for ddr buffer transfer.55 - description: Pixel clock.56 - description: Clock for the ahb bus to R/W the phy regs.57 58 clock-names:59 items:60 - const: aclk_vop61 - const: dclk_vop62 - const: hclk_vop63 64 resets:65 maxItems: 366 67 reset-names:68 items:69 - const: axi70 - const: ahb71 - const: dclk72 73 port:74 $ref: /schemas/graph.yaml#/properties/port75 76 assigned-clocks:77 maxItems: 278 79 assigned-clock-rates:80 maxItems: 281 82 iommus:83 maxItems: 184 85 power-domains:86 maxItems: 187 88required:89 - compatible90 - reg91 - interrupts92 - clocks93 - clock-names94 - resets95 - reset-names96 - port97 98additionalProperties: false99 100examples:101 - |102 #include <dt-bindings/clock/rk3288-cru.h>103 #include <dt-bindings/interrupt-controller/arm-gic.h>104 #include <dt-bindings/power/rk3288-power.h>105 vopb: vopb@ff930000 {106 compatible = "rockchip,rk3288-vop";107 reg = <0xff930000 0x19c>,108 <0xff931000 0x1000>;109 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;110 clocks = <&cru ACLK_VOP0>,111 <&cru DCLK_VOP0>,112 <&cru HCLK_VOP0>;113 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";114 power-domains = <&power RK3288_PD_VIO>;115 resets = <&cru SRST_LCDC1_AXI>,116 <&cru SRST_LCDC1_AHB>,117 <&cru SRST_LCDC1_DCLK>;118 reset-names = "axi", "ahb", "dclk";119 iommus = <&vopb_mmu>;120 vopb_out: port {121 #address-cells = <1>;122 #size-cells = <0>;123 vopb_out_edp: endpoint@0 {124 reg = <0>;125 remote-endpoint = <&edp_in_vopb>;126 };127 vopb_out_hdmi: endpoint@1 {128 reg = <1>;129 remote-endpoint = <&hdmi_in_vopb>;130 };131 };132 };133