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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)8 9maintainers:10 - Inki Dae <inki.dae@samsung.com>11 - Seung-Woo Kim <sw0312.kim@samsung.com>12 - Kyungmin Park <kyungmin.park@samsung.com>13 - Krzysztof Kozlowski <krzk@kernel.org>14 15description: |16 DECON (Display and Enhancement Controller) is the Display Controller for the17 Exynos5433 series of SoCs which transfers the image data from a video memory18 buffer to an external LCD interface.19 20properties:21 compatible:22 enum:23 - samsung,exynos5433-decon24 - samsung,exynos5433-decon-tv25 26 clocks:27 maxItems: 1128 29 clock-names:30 items:31 - const: pclk32 - const: aclk_decon33 - const: aclk_smmu_decon0x34 - const: aclk_xiu_decon0x35 - const: pclk_smmu_decon0x36 - const: aclk_smmu_decon1x37 - const: aclk_xiu_decon1x38 - const: pclk_smmu_decon1x39 - const: sclk_decon_vclk40 - const: sclk_decon_eclk41 - const: dsd42 43 interrupts:44 minItems: 345 maxItems: 446 description: |47 Interrupts depend on mode of work:48 - video mode: vsync49 - command mode: lcd_sys50 - command mode with software trigger: lcd_sys, te51 52 interrupt-names:53 minItems: 354 items:55 - const: fifo56 - const: vsync57 - const: lcd_sys58 - const: te59 60 iommus:61 maxItems: 262 63 iommu-names:64 items:65 - const: m066 - const: m167 68 ports:69 $ref: /schemas/graph.yaml#/properties/ports70 description:71 Contains a port which is connected to mic node.72 73 power-domains:74 maxItems: 175 76 reg:77 maxItems: 178 79 samsung,disp-sysreg:80 $ref: /schemas/types.yaml#/definitions/phandle81 description:82 Phandle to DISP system controller interface.83 84required:85 - compatible86 - clocks87 - clock-names88 - interrupts89 - interrupt-names90 - ports91 - reg92 93additionalProperties: false94 95examples:96 - |97 #include <dt-bindings/clock/exynos5433.h>98 #include <dt-bindings/interrupt-controller/arm-gic.h>99 100 display-controller@13800000 {101 compatible = "samsung,exynos5433-decon";102 reg = <0x13800000 0x2104>;103 clocks = <&cmu_disp CLK_PCLK_DECON>,104 <&cmu_disp CLK_ACLK_DECON>,105 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,106 <&cmu_disp CLK_ACLK_XIU_DECON0X>,107 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,108 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,109 <&cmu_disp CLK_ACLK_XIU_DECON1X>,110 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,111 <&cmu_disp CLK_SCLK_DECON_VCLK>,112 <&cmu_disp CLK_SCLK_DECON_ECLK>,113 <&cmu_disp CLK_SCLK_DSD>;114 clock-names = "pclk",115 "aclk_decon",116 "aclk_smmu_decon0x",117 "aclk_xiu_decon0x",118 "pclk_smmu_decon0x",119 "aclk_smmu_decon1x",120 "aclk_xiu_decon1x",121 "pclk_smmu_decon1x",122 "sclk_decon_vclk",123 "sclk_decon_eclk",124 "dsd";125 power-domains = <&pd_disp>;126 interrupt-names = "fifo", "vsync", "lcd_sys";127 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,128 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,129 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;130 samsung,disp-sysreg = <&syscon_disp>;131 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;132 iommu-names = "m0", "m1";133 134 ports {135 #address-cells = <1>;136 #size-cells = <0>;137 138 port@0 {139 reg = <0>;140 decon_to_mic: endpoint {141 remote-endpoint = <&mic_to_decon>;142 };143 };144 };145 };146