198 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)8 9maintainers:10 - Inki Dae <inki.dae@samsung.com>11 - Seung-Woo Kim <sw0312.kim@samsung.com>12 - Kyungmin Park <kyungmin.park@samsung.com>13 - Krzysztof Kozlowski <krzk@kernel.org>14 15properties:16 compatible:17 enum:18 - samsung,s3c2443-fimd19 - samsung,s3c6400-fimd20 - samsung,s5pv210-fimd21 - samsung,exynos3250-fimd22 - samsung,exynos4210-fimd23 - samsung,exynos5250-fimd24 - samsung,exynos5420-fimd25 26 '#address-cells':27 const: 128 29 clocks:30 maxItems: 231 32 clock-names:33 items:34 - const: sclk_fimd35 - const: fimd36 37 display-timings:38 $ref: ../panel/display-timings.yaml#39 40 i80-if-timings:41 type: object42 additionalProperties: false43 description: |44 Timing configuration for lcd i80 interface support.45 The parameters are defined as::46 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??47 : : : : :48 Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX49 | cs-setup+1 | : : :50 |<---------->| : : :51 Chip Select ???????????????|____________:____________:____________|??52 | wr-setup+1 | | wr-hold+1 |53 |<---------->| |<---------->|54 Write Enable ????????????????????????????|____________|???????????????55 | wr-active+1|56 |<---------->|57 Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--58 59 properties:60 cs-setup:61 $ref: /schemas/types.yaml#/definitions/uint3262 description:63 Clock cycles for the active period of address signal is enabled until64 chip select is enabled.65 default: 066 67 wr-active:68 $ref: /schemas/types.yaml#/definitions/uint3269 description:70 Clock cycles for the active period of CS is enabled.71 default: 172 73 wr-hold:74 $ref: /schemas/types.yaml#/definitions/uint3275 description:76 Clock cycles for the active period of CS is disabled until write77 signal is disabled.78 default: 079 80 wr-setup:81 $ref: /schemas/types.yaml#/definitions/uint3282 description:83 Clock cycles for the active period of CS signal is enabled until84 write signal is enabled.85 default: 086 87 iommus:88 minItems: 189 maxItems: 290 91 iommu-names:92 items:93 - const: m094 - const: m195 96 interrupts:97 items:98 - description: FIFO level99 - description: VSYNC100 - description: LCD system101 102 interrupt-names:103 items:104 - const: fifo105 - const: vsync106 - const: lcd_sys107 108 power-domains:109 maxItems: 1110 111 reg:112 maxItems: 1113 114 samsung,invert-vden:115 type: boolean116 description:117 Video enable signal is inverted.118 119 samsung,invert-vclk:120 type: boolean121 description:122 Video clock signal is inverted.123 124 samsung,sysreg:125 $ref: /schemas/types.yaml#/definitions/phandle126 description:127 Phandle to System Register syscon.128 129 '#size-cells':130 const: 0131 132patternProperties:133 "^port@[0-4]+$":134 $ref: /schemas/graph.yaml#/properties/port135 description: |136 Contains ports with port with index::137 0 - for CAMIF0 input,138 1 - for CAMIF1 input,139 2 - for CAMIF2 input,140 3 - for parallel output,141 4 - for write-back interface142 143required:144 - compatible145 - clocks146 - clock-names147 - interrupts148 - interrupt-names149 - reg150 151allOf:152 - if:153 properties:154 compatible:155 contains:156 const: samsung,exynos5420-fimd157 then:158 properties:159 iommus:160 minItems: 2161 maxItems: 2162 163additionalProperties: false164 165examples:166 - |167 #include <dt-bindings/clock/exynos4.h>168 169 fimd@11c00000 {170 compatible = "samsung,exynos4210-fimd";171 interrupt-parent = <&combiner>;172 reg = <0x11c00000 0x20000>;173 interrupt-names = "fifo", "vsync", "lcd_sys";174 interrupts = <11 0>, <11 1>, <11 2>;175 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;176 clock-names = "sclk_fimd", "fimd";177 power-domains = <&pd_lcd0>;178 iommus = <&sysmmu_fimd0>;179 samsung,sysreg = <&sys_reg>;180 181 #address-cells = <1>;182 #size-cells = <0>;183 184 samsung,invert-vden;185 samsung,invert-vclk;186 187 pinctrl-0 = <&lcd_clk>, <&lcd_data24>;188 pinctrl-names = "default";189 190 port@3 {191 reg = <3>;192 193 fimd_dpi_ep: endpoint {194 remote-endpoint = <&lcd_ep>;195 };196 };197 };198