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1ARC PGU2 3This is a display controller found on several development boards produced4by Synopsys. The ARC PGU is an RGB streamer that reads the data from a5framebuffer and sends it to a single digital encoder (usually HDMI).6 7Required properties:8 - compatible: "snps,arcpgu"9 - reg: Physical base address and length of the controller's registers.10 - clocks: A list of phandle + clock-specifier pairs, one for each11 entry in 'clock-names'.12 - clock-names: A list of clock names. For ARC PGU it should contain:13 - "pxlclk" for the clock feeding the output PLL of the controller.14 15Required sub-nodes:16 - port: The PGU connection to an encoder chip.17 18Example:19 20/ {21 ...22 23 pgu@XXXXXXXX {24 compatible = "snps,arcpgu";25 reg = <0xXXXXXXXX 0x400>;26 clocks = <&clock_node>;27 clock-names = "pxlclk";28 29 port {30 pgu_output: endpoint {31 remote-endpoint = <&hdmi_enc_input>;32 };33 };34 };35};36