86 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra186 (and later) Display Controller8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13properties:14 $nodename:15 pattern: "^display@[0-9a-f]+$"16 17 compatible:18 enum:19 - nvidia,tegra186-dc20 - nvidia,tegra194-dc21 22 reg:23 maxItems: 124 25 interrupts:26 maxItems: 127 28 clocks:29 items:30 - description: display controller pixel clock31 32 clock-names:33 items:34 - const: dc35 36 resets:37 items:38 - description: display controller reset39 40 reset-names:41 items:42 - const: dc43 44 power-domains:45 maxItems: 146 47 iommus:48 maxItems: 149 50 interconnects:51 description: Description of the interconnect paths for the52 display controller; see ../interconnect/interconnect.txt53 for details.54 55 interconnect-names:56 items:57 - const: dma-mem # read-058 - const: read-159 60 nvidia,outputs:61 description: A list of phandles of outputs that this display62 controller can drive.63 $ref: /schemas/types.yaml#/definitions/phandle-array64 65 nvidia,head:66 description: The number of the display controller head. This67 is used to setup the various types of output to receive68 video data from the given head.69 $ref: /schemas/types.yaml#/definitions/uint3270 71additionalProperties: false72 73required:74 - compatible75 - reg76 - interrupts77 - clocks78 - clock-names79 - resets80 - reset-names81 - power-domains82 - nvidia,outputs83 - nvidia,head84 85# see nvidia,tegra186-display.yaml for examples86