183 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra Display Controller8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13properties:14 $nodename:15 pattern: "^dc@[0-9a-f]+$"16 17 compatible:18 oneOf:19 - enum:20 - nvidia,tegra20-dc21 - nvidia,tegra30-dc22 - nvidia,tegra114-dc23 - nvidia,tegra124-dc24 - nvidia,tegra210-dc25 26 - items:27 - const: nvidia,tegra124-dc28 - const: nvidia,tegra132-dc29 30 reg:31 maxItems: 132 33 interrupts:34 maxItems: 135 36 clocks:37 minItems: 138 items:39 - description: display controller pixel clock40 - description: parent clock # optional41 42 clock-names:43 minItems: 144 items:45 - const: dc46 - const: parent # optional47 48 resets:49 items:50 - description: module reset51 52 reset-names:53 items:54 - const: dc55 56 interconnect-names: true57 interconnects: true58 59 iommus:60 maxItems: 161 62 operating-points-v2: true63 64 power-domains:65 items:66 - description: phandle to the core power domain67 68 memory-region: true69 70 nvidia,head:71 $ref: /schemas/types.yaml#/definitions/uint3272 description: The number of the display controller head. This is used to setup the various73 types of output to receive video data from the given head.74 75 nvidia,outputs:76 $ref: /schemas/types.yaml#/definitions/phandle-array77 description: A list of phandles of outputs that this display controller can drive.78 79 rgb:80 type: object81 82allOf:83 - if:84 properties:85 compatible:86 contains:87 enum:88 - nvidia,tegra20-dc89 - nvidia,tegra30-dc90 - nvidia,tegra114-dc91 then:92 properties:93 interconnects:94 items:95 - description: window A memory client96 - description: window B memory client97 - description: window B memory client (vertical filter)98 - description: window C memory client99 - description: cursor memory client100 101 interconnect-names:102 items:103 - const: wina104 - const: winb105 - const: winb-vfilter106 - const: winc107 - const: cursor108 109 rgb:110 description: Each display controller node has a child node, named "rgb", that represents111 the RGB output associated with the controller.112 type: object113 properties:114 nvidia,ddc-i2c-bus:115 $ref: /schemas/types.yaml#/definitions/phandle116 description: phandle of an I2C controller used for DDC EDID probing117 118 nvidia,hpd-gpio:119 description: specifies a GPIO used for hotplug detection120 maxItems: 1121 122 nvidia,edid:123 $ref: /schemas/types.yaml#/definitions/uint8-array124 description: supplies a binary EDID blob125 126 nvidia,panel:127 $ref: /schemas/types.yaml#/definitions/phandle128 description: phandle of a display panel129 130 - if:131 properties:132 compatible:133 contains:134 enum:135 - nvidia,tegra124-dc136 then:137 properties:138 interconnects:139 minItems: 4140 items:141 - description: window A memory client142 - description: window B memory client143 - description: window C memory client144 - description: cursor memory client145 - description: window D memory client146 - description: window T memory client147 148 interconnect-names:149 minItems: 4150 items:151 - const: wina152 - const: winb153 - const: winc154 - const: cursor155 - const: wind156 - const: wint157 158additionalProperties: false159 160required:161 - compatible162 - reg163 - interrupts164 - clocks165 - clock-names166 - resets167 - reset-names168 169examples:170 - |171 #include <dt-bindings/clock/tegra20-car.h>172 #include <dt-bindings/interrupt-controller/arm-gic.h>173 174 dc@54200000 {175 compatible = "nvidia,tegra20-dc";176 reg = <0x54200000 0x00040000>;177 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;178 clocks = <&tegra_car TEGRA20_CLK_DISP1>;179 clock-names = "dc";180 resets = <&tegra_car 27>;181 reset-names = "dc";182 };183