68 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra ISP processor8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13properties:14 compatible:15 enum:16 - nvidia,tegra20-isp17 - nvidia,tegra30-isp18 - nvidia,tegra210-isp19 20 reg:21 maxItems: 122 23 interrupts:24 maxItems: 125 26 clocks:27 items:28 - description: module clock29 30 resets:31 items:32 - description: module reset33 34 reset-names:35 items:36 - const: isp37 38 iommus:39 maxItems: 140 41 interconnects:42 items:43 - description: memory write client44 45 interconnect-names:46 items:47 - const: dma-mem # write48 49 power-domains:50 items:51 - description: phandle to the VENC or core power domain52 53additionalProperties: false54 55examples:56 - |57 #include <dt-bindings/clock/tegra20-car.h>58 #include <dt-bindings/interrupt-controller/arm-gic.h>59 60 isp@54100000 {61 compatible = "nvidia,tegra20-isp";62 reg = <0x54100000 0x00040000>;63 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;64 clocks = <&tegra_car TEGRA20_CLK_ISP>;65 resets = <&tegra_car 23>;66 reset-names = "isp";67 };68