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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright 2019 Texas Instruments Incorporated3%YAML 1.24---5$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Texas Instruments AM65x Display Subsystem9 10maintainers:11 - Jyri Sarha <jsarha@ti.com>12 - Tomi Valkeinen <tomi.valkeinen@ti.com>13 14description: |15 The AM625 and AM65x TI Keystone Display SubSystem with two output16 ports and two video planes. In AM65x DSS, the first video port17 supports 1 OLDI TX and in AM625 DSS, the first video port output is18 internally routed to 2 OLDI TXes. The second video port supports DPI19 format. The first plane is full video plane with all features and the20 second is a "lite plane" without scaling support.21 22properties:23 compatible:24 enum:25 - ti,am625-dss26 - ti,am62a7,dss27 - ti,am65x-dss28 29 reg:30 description:31 Addresses to each DSS memory region described in the SoC's TRM.32 items:33 - description: common DSS register area34 - description: VIDL1 light video plane35 - description: VID video plane36 - description: OVR1 overlay manager for vp137 - description: OVR2 overlay manager for vp238 - description: VP1 video port 139 - description: VP2 video port 240 - description: common1 DSS register area41 42 reg-names:43 items:44 - const: common45 - const: vidl146 - const: vid47 - const: ovr148 - const: ovr249 - const: vp150 - const: vp251 - const: common152 53 clocks:54 items:55 - description: fck DSS functional clock56 - description: vp1 Video Port 1 pixel clock57 - description: vp2 Video Port 2 pixel clock58 59 clock-names:60 items:61 - const: fck62 - const: vp163 - const: vp264 65 assigned-clocks:66 minItems: 167 maxItems: 368 69 assigned-clock-parents:70 minItems: 171 maxItems: 372 73 interrupts:74 maxItems: 175 76 power-domains:77 maxItems: 178 description: phandle to the associated power domain79 80 dma-coherent:81 type: boolean82 83 ports:84 $ref: /schemas/graph.yaml#/properties/ports85 86 properties:87 port@0:88 $ref: /schemas/graph.yaml#/properties/port89 description:90 For AM65x DSS, the OLDI output port node from video port 1.91 For AM625 DSS, the internal DPI output port node from video92 port 1.93 For AM62A7 DSS, the port is tied off inside the SoC.94 95 port@1:96 $ref: /schemas/graph.yaml#/properties/port97 description:98 The DSS DPI output port node from video port 299 100 ti,am65x-oldi-io-ctrl:101 $ref: /schemas/types.yaml#/definitions/phandle102 description:103 phandle to syscon device node mapping OLDI IO_CTRL registers.104 The mapped range should point to OLDI_DAT0_IO_CTRL, map it and105 following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,106 and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI107 interface to work.108 109 max-memory-bandwidth:110 $ref: /schemas/types.yaml#/definitions/uint32111 description:112 Input memory (from main memory to dispc) bandwidth limit in113 bytes per second114 115allOf:116 - if:117 properties:118 compatible:119 contains:120 const: ti,am62a7-dss121 then:122 properties:123 ports:124 properties:125 port@0: false126 127required:128 - compatible129 - reg130 - reg-names131 - clocks132 - clock-names133 - interrupts134 - ports135 136additionalProperties: false137 138examples:139 - |140 #include <dt-bindings/interrupt-controller/arm-gic.h>141 #include <dt-bindings/interrupt-controller/irq.h>142 #include <dt-bindings/soc/ti,sci_pm_domain.h>143 144 dss: dss@4a00000 {145 compatible = "ti,am65x-dss";146 reg = <0x04a00000 0x1000>, /* common */147 <0x04a02000 0x1000>, /* vidl1 */148 <0x04a06000 0x1000>, /* vid */149 <0x04a07000 0x1000>, /* ovr1 */150 <0x04a08000 0x1000>, /* ovr2 */151 <0x04a0a000 0x1000>, /* vp1 */152 <0x04a0b000 0x1000>, /* vp2 */153 <0x04a01000 0x1000>; /* common1 */154 reg-names = "common", "vidl1", "vid",155 "ovr1", "ovr2", "vp1", "vp2", "common1";156 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;157 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;158 clocks = <&k3_clks 67 1>,159 <&k3_clks 216 1>,160 <&k3_clks 67 2>;161 clock-names = "fck", "vp1", "vp2";162 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;163 ports {164 #address-cells = <1>;165 #size-cells = <0>;166 port@0 {167 reg = <0>;168 oldi_out0: endpoint {169 remote-endpoint = <&lcd_in0>;170 };171 };172 };173 };174