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1Texas Instruments DRA7x Display Subsystem2=========================================3 4See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic5description about OMAP Display Subsystem bindings.6 7DSS Core8--------9 10Required properties:11- compatible: "ti,dra7-dss"12- reg: address and length of the register spaces for 'dss'13- ti,hwmods: "dss_core"14- clocks: handle to fclk15- clock-names: "fck"16- syscon: phandle to control module core syscon node17 18Optional properties:19 20Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties21can be used to describe the video PLLs:22 23- reg: address and length of the register spaces for 'pll1_clkctrl',24 'pll1', 'pll2_clkctrl', 'pll2'25- clocks: handle to video1 pll clock and video2 pll clock26- clock-names: "video1_clk" and "video2_clk"27 28Required nodes:29- DISPC30 31Optional nodes:32- DSS Submodules: HDMI33- Video port for DPI output34 35DPI Endpoint required properties:36- data-lines: number of lines used37 38 39DISPC40-----41 42Required properties:43- compatible: "ti,dra7-dispc"44- reg: address and length of the register space45- ti,hwmods: "dss_dispc"46- interrupts: the DISPC interrupt47- clocks: handle to fclk48- clock-names: "fck"49 50Optional properties:51- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit52 in bytes per second53 54 55HDMI56----57 58Required properties:59- compatible: "ti,dra7-hdmi"60- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',61 'core'62- reg-names: "wp", "pll", "phy", "core"63- interrupts: the HDMI interrupt line64- ti,hwmods: "dss_hdmi"65- vdda-supply: vdda power supply66- clocks: handles to fclk and pll clock67- clock-names: "fck", "sys_clk"68 69Optional nodes:70- Video port for HDMI output71 72HDMI Endpoint optional properties:73- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,74 D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)75