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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright 2019 Texas Instruments Incorporated3%YAML 1.24---5$id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Texas Instruments J721E Display Subsystem9 10maintainers:11 - Jyri Sarha <jsarha@ti.com>12 - Tomi Valkeinen <tomi.valkeinen@ti.com>13 14description: |15 The J721E TI Keystone Display SubSystem with four output ports and16 four video planes. There is two full video planes and two "lite17 planes" without scaling support. The video ports can be connected to18 the SoC's DPI pins or to integrated display bridges on the SoC.19 20properties:21 compatible:22 const: ti,j721e-dss23 24 reg:25 items:26 - description: common_m DSS Master common27 - description: common_s0 DSS Shared common 028 - description: common_s1 DSS Shared common 129 - description: common_s2 DSS Shared common 230 - description: VIDL1 light video plane 131 - description: VIDL2 light video plane 232 - description: VID1 video plane 133 - description: VID1 video plane 234 - description: OVR1 overlay manager for vp135 - description: OVR2 overlay manager for vp236 - description: OVR3 overlay manager for vp337 - description: OVR4 overlay manager for vp438 - description: VP1 video port 139 - description: VP2 video port 240 - description: VP3 video port 341 - description: VP4 video port 442 - description: WB Write Back43 44 reg-names:45 items:46 - const: common_m47 - const: common_s048 - const: common_s149 - const: common_s250 - const: vidl151 - const: vidl252 - const: vid153 - const: vid254 - const: ovr155 - const: ovr256 - const: ovr357 - const: ovr458 - const: vp159 - const: vp260 - const: vp361 - const: vp462 - const: wb63 64 clocks:65 items:66 - description: fck DSS functional clock67 - description: vp1 Video Port 1 pixel clock68 - description: vp2 Video Port 2 pixel clock69 - description: vp3 Video Port 3 pixel clock70 - description: vp4 Video Port 4 pixel clock71 72 clock-names:73 items:74 - const: fck75 - const: vp176 - const: vp277 - const: vp378 - const: vp479 80 assigned-clocks:81 minItems: 182 maxItems: 583 84 assigned-clock-parents:85 minItems: 186 maxItems: 587 88 interrupts:89 items:90 - description: common_m DSS Master common91 - description: common_s0 DSS Shared common 092 - description: common_s1 DSS Shared common 193 - description: common_s2 DSS Shared common 294 95 interrupt-names:96 items:97 - const: common_m98 - const: common_s099 - const: common_s1100 - const: common_s2101 102 power-domains:103 maxItems: 1104 description: phandle to the associated power domain105 106 dma-coherent:107 type: boolean108 109 ports:110 $ref: /schemas/graph.yaml#/properties/ports111 112 properties:113 port@0:114 $ref: /schemas/graph.yaml#/properties/port115 description:116 The output port node form video port 1117 118 port@1:119 $ref: /schemas/graph.yaml#/properties/port120 description:121 The output port node from video port 2122 123 port@2:124 $ref: /schemas/graph.yaml#/properties/port125 description:126 The output port node from video port 3127 128 port@3:129 $ref: /schemas/graph.yaml#/properties/port130 description:131 The output port node from video port 4132 133 max-memory-bandwidth:134 $ref: /schemas/types.yaml#/definitions/uint32135 description:136 Input memory (from main memory to dispc) bandwidth limit in137 bytes per second138 139required:140 - compatible141 - reg142 - reg-names143 - clocks144 - clock-names145 - interrupts146 - interrupt-names147 - ports148 149additionalProperties: false150 151examples:152 - |153 #include <dt-bindings/interrupt-controller/arm-gic.h>154 #include <dt-bindings/interrupt-controller/irq.h>155 #include <dt-bindings/soc/ti,sci_pm_domain.h>156 157 dss: dss@4a00000 {158 compatible = "ti,j721e-dss";159 reg = <0x04a00000 0x10000>, /* common_m */160 <0x04a10000 0x10000>, /* common_s0*/161 <0x04b00000 0x10000>, /* common_s1*/162 <0x04b10000 0x10000>, /* common_s2*/163 <0x04a20000 0x10000>, /* vidl1 */164 <0x04a30000 0x10000>, /* vidl2 */165 <0x04a50000 0x10000>, /* vid1 */166 <0x04a60000 0x10000>, /* vid2 */167 <0x04a70000 0x10000>, /* ovr1 */168 <0x04a90000 0x10000>, /* ovr2 */169 <0x04ab0000 0x10000>, /* ovr3 */170 <0x04ad0000 0x10000>, /* ovr4 */171 <0x04a80000 0x10000>, /* vp1 */172 <0x04aa0000 0x10000>, /* vp2 */173 <0x04ac0000 0x10000>, /* vp3 */174 <0x04ae0000 0x10000>, /* vp4 */175 <0x04af0000 0x10000>; /* wb */176 reg-names = "common_m", "common_s0",177 "common_s1", "common_s2",178 "vidl1", "vidl2","vid1","vid2",179 "ovr1", "ovr2", "ovr3", "ovr4",180 "vp1", "vp2", "vp3", "vp4",181 "wb";182 clocks = <&k3_clks 152 0>,183 <&k3_clks 152 1>,184 <&k3_clks 152 4>,185 <&k3_clks 152 9>,186 <&k3_clks 152 13>;187 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";188 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;189 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,190 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,191 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,192 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;193 interrupt-names = "common_m",194 "common_s0",195 "common_s1",196 "common_s2";197 ports {198 #address-cells = <1>;199 #size-cells = <0>;200 port@0 {201 reg = <0>;202 203 dpi_out_0: endpoint {204 remote-endpoint = <&dp_bridge_input>;205 };206 };207 };208 };209