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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx ZynqMP DisplayPort Subsystem8 9description: |10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)11 implements the display and audio pipelines based on the DisplayPort v1.212 standard. The subsystem includes multiple functional blocks as below:13 14 +------------------------------------------------------------+15 +--------+ | +----------------+ +-----------+ |16 | DPDMA | --->| | --> | Video | Video +-------------+ |17 | 4x vid | | | | | Rendering | -+--> | | | +------+18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+20 | | and STC | +-----------+ | | Controller | | +------+21 Live Video --->| | --> | Audio | Audio | |---> | PHY1 |22 | | | | Mixer | --+-> | | | +------+23 Live Audio --->| | --> | | || +-------------+ |24 | +----------------+ +-----------+ || |25 +---------------------------------------||-------------------+26 vv27 Blended Video and28 Mixed Audio to PL29 30 The Buffer Manager interacts with external interface such as DMA engines or31 live audio/video streams from the programmable logic. The Video Rendering32 Pipeline blends the video and graphics layers and performs colorspace33 conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort34 Source Controller handles the DisplayPort protocol and connects to external35 PHYs.36 37 The subsystem supports 2 video and 2 audio streams, and various pixel formats38 and depths up to 4K@30 resolution.39 40 Please refer to "Zynq UltraScale+ Device Technical Reference Manual"41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)42 for more details.43 44maintainers:45 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>46 47properties:48 compatible:49 const: xlnx,zynqmp-dpsub-1.750 51 reg:52 maxItems: 453 reg-names:54 items:55 - const: dp56 - const: blend57 - const: av_buf58 - const: aud59 60 interrupts:61 maxItems: 162 63 clocks:64 description:65 The APB clock and at least one video clock are mandatory, the audio clock66 is optional.67 minItems: 268 items:69 - description: dp_apb_clk is the APB clock70 - description: dp_aud_clk is the Audio clock71 - description:72 dp_vtc_pixel_clk_in is the non-live video clock (from Processing73 System)74 - description:75 dp_live_video_in_clk is the live video clock (from Programmable76 Logic)77 clock-names:78 oneOf:79 - minItems: 280 items:81 - const: dp_apb_clk82 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]83 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]84 - minItems: 385 items:86 - const: dp_apb_clk87 - const: dp_aud_clk88 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]89 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]90 91 power-domains:92 maxItems: 193 94 resets:95 maxItems: 196 97 dmas:98 items:99 - description: Video layer, plane 0 (RGB or luma)100 - description: Video layer, plane 1 (U/V or U)101 - description: Video layer, plane 2 (V)102 - description: Graphics layer103 dma-names:104 items:105 - const: vid0106 - const: vid1107 - const: vid2108 - const: gfx0109 110 phys:111 description: PHYs for the DP data lanes112 minItems: 1113 maxItems: 2114 phy-names:115 minItems: 1116 items:117 - const: dp-phy0118 - const: dp-phy1119 120 ports:121 $ref: /schemas/graph.yaml#/properties/ports122 description: |123 Connections to the programmable logic and the DisplayPort PHYs. Each port124 shall have a single endpoint.125 126 properties:127 port@0:128 $ref: /schemas/graph.yaml#/properties/port129 description: The live video input from the programmable logic130 131 port@1:132 $ref: /schemas/graph.yaml#/properties/port133 description: The live graphics input from the programmable logic134 135 port@2:136 $ref: /schemas/graph.yaml#/properties/port137 description: The live audio input from the programmable logic138 139 port@3:140 $ref: /schemas/graph.yaml#/properties/port141 description: The blended video output to the programmable logic142 143 port@4:144 $ref: /schemas/graph.yaml#/properties/port145 description: The mixed audio output to the programmable logic146 147 port@5:148 $ref: /schemas/graph.yaml#/properties/port149 description: The DisplayPort output150 151 required:152 - port@0153 - port@1154 - port@2155 - port@3156 - port@4157 - port@5158 159required:160 - compatible161 - reg162 - reg-names163 - interrupts164 - clocks165 - clock-names166 - power-domains167 - resets168 - dmas169 - dma-names170 - phys171 - phy-names172 - ports173 174additionalProperties: false175 176examples:177 - |178 #include <dt-bindings/phy/phy.h>179 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>180 181 display@fd4a0000 {182 compatible = "xlnx,zynqmp-dpsub-1.7";183 reg = <0xfd4a0000 0x1000>,184 <0xfd4aa000 0x1000>,185 <0xfd4ab000 0x1000>,186 <0xfd4ac000 0x1000>;187 reg-names = "dp", "blend", "av_buf", "aud";188 interrupts = <0 119 4>;189 interrupt-parent = <&gic>;190 191 clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";192 clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;193 194 power-domains = <&pd_dp>;195 resets = <&reset ZYNQMP_RESET_DP>;196 197 dma-names = "vid0", "vid1", "vid2", "gfx0";198 dmas = <&xlnx_dpdma 0>,199 <&xlnx_dpdma 1>,200 <&xlnx_dpdma 2>,201 <&xlnx_dpdma 3>;202 203 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,204 <&psgtr 0 PHY_TYPE_DP 1 3>;205 206 phy-names = "dp-phy0", "dp-phy1";207 208 ports {209 #address-cells = <1>;210 #size-cells = <0>;211 212 port@0 {213 reg = <0>;214 };215 port@1 {216 reg = <1>;217 };218 port@2 {219 reg = <2>;220 };221 port@3 {222 reg = <3>;223 };224 port@4 {225 reg = <4>;226 };227 port@5 {228 reg = <5>;229 dpsub_dp_out: endpoint {230 remote-endpoint = <&dp_connector>;231 };232 };233 };234 };235 236...237