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1Analog Devices AXI-DMAC DMA controller2 3Required properties:4 - compatible: Must be "adi,axi-dmac-1.00.a".5 - reg: Specification for the controllers memory mapped register map.6 - interrupts: Specification for the controllers interrupt.7 - clocks: Phandle and specifier to the controllers AXI interface clock8 - #dma-cells: Must be 1.9 10Required sub-nodes:11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For12 the channel sub-nodes the following bindings apply. They must match the13 configuration options of the peripheral as it was instantiated.14 15Required properties for adi,channels sub-node:16 - #size-cells: Must be 017 - #address-cells: Must be 118 19Required channel sub-node properties:20 - reg: Which channel this node refers to.21 - adi,source-bus-width,22 adi,destination-bus-width: Width of the source or destination bus in bits.23 - adi,source-bus-type,24 adi,destination-bus-type: Type of the source or destination bus. Must be one25 of the following:26 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface27 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface28 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface29 30Deprecated optional channel properties:31 - adi,length-width: Width of the DMA transfer length register.32 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA33 transfers.34 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.35 36DMA clients connected to the AXI-DMAC DMA controller must use the format37described in the dma.txt file using a one-cell specifier. The value of the38specifier refers to the DMA channel index.39 40Example:41 42dma: dma@7c420000 {43 compatible = "adi,axi-dmac-1.00.a";44 reg = <0x7c420000 0x10000>;45 interrupts = <0 57 0>;46 clocks = <&clkc 16>;47 #dma-cells = <1>;48 49 adi,channels {50 #size-cells = <0>;51 #address-cells = <1>;52 53 dma-channel@0 {54 reg = <0>;55 adi,source-bus-width = <32>;56 adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;57 adi,destination-bus-width = <64>;58 adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;59 };60 };61};62