64 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Altera mSGDMA IP core8 9maintainers:10 - Olivier Dautricourt <olivierdautricourt@gmail.com>11 12description: |13 Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)14 intellectual property (IP)15 16allOf:17 - $ref: dma-controller.yaml#18 19properties:20 compatible:21 const: altr,socfpga-msgdma22 23 reg:24 items:25 - description: Control and Status Register Slave Port26 - description: Descriptor Slave Port27 - description: Response Slave Port (Optional)28 minItems: 229 30 reg-names:31 items:32 - const: csr33 - const: desc34 - const: resp35 minItems: 236 37 interrupts:38 maxItems: 139 40 "#dma-cells":41 const: 142 description:43 The cell identifies the channel id (must be 0)44 45required:46 - compatible47 - reg48 - reg-names49 - interrupts50 51unevaluatedProperties: false52 53examples:54 - |55 #include <dt-bindings/interrupt-controller/irq.h>56 57 msgdma_controller: dma-controller@ff200b00 {58 compatible = "altr,socfpga-msgdma";59 reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;60 reg-names = "csr", "desc", "resp";61 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;62 #dma-cells = <1>;63 };64