303 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/fsl,edma.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale enhanced Direct Memory Access(eDMA) Controller8 9description: |10 The eDMA channels have multiplex capability by programmable11 memory-mapped registers. channels are split into two groups, called12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed13 by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.14 15maintainers:16 - Peng Fan <peng.fan@nxp.com>17 18properties:19 compatible:20 oneOf:21 - enum:22 - fsl,vf610-edma23 - fsl,imx7ulp-edma24 - fsl,imx8qm-edma25 - fsl,imx8ulp-edma26 - fsl,imx93-edma327 - fsl,imx93-edma428 - fsl,imx95-edma529 - items:30 - const: fsl,ls1028a-edma31 - const: fsl,vf610-edma32 33 reg:34 minItems: 135 maxItems: 336 37 interrupts:38 minItems: 139 maxItems: 6440 41 interrupt-names:42 minItems: 143 maxItems: 6444 45 "#dma-cells":46 description: |47 Specifies the number of cells needed to encode an DMA channel.48 49 Encode for cells number 2:50 cell 0: index of dma channel mux instance.51 cell 1: peripheral dma request id.52 53 Encode for cells number 3:54 cell 0: peripheral dma request id.55 cell 1: dma channel priority.56 cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h57 enum:58 - 259 - 360 61 dma-channels:62 minimum: 163 maximum: 6464 65 clocks:66 minItems: 167 maxItems: 3368 69 clock-names:70 minItems: 171 maxItems: 3372 73 power-domains:74 description:75 The number of power domains matches the number of channels, arranged76 in ascending order according to their associated DMA channels.77 minItems: 178 maxItems: 6479 80 big-endian:81 description: |82 If present registers and hardware scatter/gather descriptors of the83 eDMA are implemented in big endian mode, otherwise in little mode.84 type: boolean85 86required:87 - "#dma-cells"88 - compatible89 - reg90 - interrupts91 - dma-channels92 93allOf:94 - $ref: dma-controller.yaml#95 - if:96 properties:97 compatible:98 contains:99 enum:100 - fsl,imx8qm-edma101 - fsl,imx93-edma3102 - fsl,imx93-edma4103 - fsl,imx95-edma5104 then:105 properties:106 "#dma-cells":107 const: 3108 # It is not necessary to write the interrupt name for each channel.109 # instead, you can simply maintain the sequential IRQ numbers as110 # defined for the DMA channels.111 interrupt-names: false112 clock-names:113 items:114 - const: dma115 clocks:116 maxItems: 1117 118 - if:119 properties:120 compatible:121 contains:122 const: fsl,vf610-edma123 then:124 properties:125 clocks:126 minItems: 2127 maxItems: 2128 clock-names:129 items:130 - const: dmamux0131 - const: dmamux1132 interrupts:133 minItems: 2134 maxItems: 2135 interrupt-names:136 items:137 - const: edma-tx138 - const: edma-err139 reg:140 minItems: 2141 maxItems: 3142 "#dma-cells":143 const: 2144 dma-channels:145 const: 32146 147 - if:148 properties:149 compatible:150 contains:151 const: fsl,imx7ulp-edma152 then:153 properties:154 clock:155 minItems: 2156 maxItems: 2157 clock-names:158 items:159 - const: dma160 - const: dmamux0161 interrupts:162 minItems: 2163 maxItems: 17164 reg:165 minItems: 2166 maxItems: 2167 "#dma-cells":168 const: 2169 dma-channels:170 const: 32171 172 - if:173 properties:174 compatible:175 contains:176 const: fsl,imx8ulp-edma177 then:178 properties:179 clocks:180 minItems: 33181 clock-names:182 minItems: 33183 items:184 oneOf:185 - const: dma186 - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"187 188 interrupt-names: false189 interrupts:190 minItems: 32191 "#dma-cells":192 const: 3193 194 - if:195 properties:196 compatible:197 contains:198 enum:199 - fsl,vf610-edma200 - fsl,imx7ulp-edma201 - fsl,imx93-edma3202 - fsl,imx93-edma4203 - fsl,imx95-edma5204 - fsl,imx8ulp-edma205 - fsl,ls1028a-edma206 then:207 required:208 - clocks209 210 - if:211 properties:212 compatible:213 contains:214 enum:215 - fsl,imx8qm-adma216 - fsl,imx8qm-edma217 then:218 required:219 - power-domains220 else:221 properties:222 power-domains: false223 224unevaluatedProperties: false225 226examples:227 - |228 #include <dt-bindings/interrupt-controller/arm-gic.h>229 #include <dt-bindings/clock/vf610-clock.h>230 231 edma0: dma-controller@40018000 {232 #dma-cells = <2>;233 compatible = "fsl,vf610-edma";234 reg = <0x40018000 0x2000>,235 <0x40024000 0x1000>,236 <0x40025000 0x1000>;237 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,238 <0 9 IRQ_TYPE_LEVEL_HIGH>;239 interrupt-names = "edma-tx", "edma-err";240 dma-channels = <32>;241 clock-names = "dmamux0", "dmamux1";242 clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;243 };244 245 - |246 #include <dt-bindings/interrupt-controller/arm-gic.h>247 #include <dt-bindings/clock/imx7ulp-clock.h>248 249 edma1: dma-controller@40080000 {250 #dma-cells = <2>;251 compatible = "fsl,imx7ulp-edma";252 reg = <0x40080000 0x2000>,253 <0x40210000 0x1000>;254 dma-channels = <32>;255 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,256 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,257 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,258 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,259 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,260 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,261 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,262 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,263 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,264 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,265 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,266 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,267 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,268 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,269 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,270 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,271 /* last is eDMA2-ERR interrupt */272 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;273 clock-names = "dma", "dmamux0";274 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;275 };276 277 - |278 #include <dt-bindings/interrupt-controller/arm-gic.h>279 #include <dt-bindings/firmware/imx/rsrc.h>280 281 dma-controller@5a9f0000 {282 compatible = "fsl,imx8qm-edma";283 reg = <0x5a9f0000 0x90000>;284 #dma-cells = <3>;285 dma-channels = <8>;286 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,287 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,288 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,289 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,290 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,291 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,292 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,293 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;294 power-domains = <&pd IMX_SC_R_DMA_3_CH0>,295 <&pd IMX_SC_R_DMA_3_CH1>,296 <&pd IMX_SC_R_DMA_3_CH2>,297 <&pd IMX_SC_R_DMA_3_CH3>,298 <&pd IMX_SC_R_DMA_3_CH4>,299 <&pd IMX_SC_R_DMA_3_CH5>,300 <&pd IMX_SC_R_DMA_3_CH6>,301 <&pd IMX_SC_R_DMA_3_CH7>;302 };303