152 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX8 9maintainers:10 - Joy Zou <joy.zou@nxp.com>11 12allOf:13 - $ref: dma-controller.yaml#14 15properties:16 compatible:17 oneOf:18 - items:19 - enum:20 - fsl,imx50-sdma21 - fsl,imx51-sdma22 - fsl,imx53-sdma23 - fsl,imx6q-sdma24 - fsl,imx7d-sdma25 - const: fsl,imx35-sdma26 - items:27 - enum:28 - fsl,imx6sx-sdma29 - fsl,imx6sl-sdma30 - const: fsl,imx6q-sdma31 - items:32 - const: fsl,imx6ul-sdma33 - const: fsl,imx6q-sdma34 - const: fsl,imx35-sdma35 - items:36 - const: fsl,imx6sll-sdma37 - const: fsl,imx6ul-sdma38 - items:39 - const: fsl,imx8mq-sdma40 - const: fsl,imx7d-sdma41 - items:42 - enum:43 - fsl,imx8mp-sdma44 - fsl,imx8mn-sdma45 - fsl,imx8mm-sdma46 - const: fsl,imx8mq-sdma47 - items:48 - enum:49 - fsl,imx25-sdma50 - fsl,imx31-sdma51 - fsl,imx35-sdma52 reg:53 maxItems: 154 55 interrupts:56 maxItems: 157 58 fsl,sdma-ram-script-name:59 $ref: /schemas/types.yaml#/definitions/string60 description: Should contain the full path of SDMA RAM scripts firmware.61 62 "#dma-cells":63 const: 364 description: |65 The first cell: request/event ID66 67 The second cell: peripheral types ID68 enum:69 - MCU domain SSI: 070 - Shared SSI: 171 - MMC: 272 - SDHC: 373 - MCU domain UART: 474 - Shared UART: 575 - FIRI: 676 - MCU domain CSPI: 777 - Shared CSPI: 878 - SIM: 979 - ATA: 1080 - CCM: 1181 - External peripheral: 1282 - Memory Stick Host Controller: 1383 - Shared Memory Stick Host Controller: 1484 - DSP: 1585 - Memory: 1686 - FIFO type Memory: 1787 - SPDIF: 1888 - IPU Memory: 1989 - ASRC: 2090 - ESAI: 2191 - SSI Dual FIFO: 2292 description: needs firmware more than ver 293 - Shared ASRC: 2394 - SAI: 2495 - Multi SAI: 2596 - HDMI Audio: 2697 - I2C: 2798 99 The third cell: transfer priority ID100 enum:101 - High: 0102 - Medium: 1103 - Low: 2104 105 gpr:106 $ref: /schemas/types.yaml#/definitions/phandle107 description: The phandle to the General Purpose Register (GPR) node108 109 fsl,sdma-event-remap:110 $ref: /schemas/types.yaml#/definitions/uint32-matrix111 maxItems: 2112 items:113 items:114 - description: GPR register offset115 - description: GPR register shift116 - description: GPR register value117 description: |118 Register bits of sdma event remap, the format is <reg shift val>.119 The order is <RX>, <TX>.120 121 clocks:122 maxItems: 2123 124 clock-names:125 items:126 - const: ipg127 - const: ahb128 129 iram:130 $ref: /schemas/types.yaml#/definitions/phandle131 description: The phandle to the On-chip RAM (OCRAM) node.132 133required:134 - compatible135 - reg136 - interrupts137 - fsl,sdma-ram-script-name138 139additionalProperties: false140 141examples:142 - |143 sdma: dma-controller@83fb0000 {144 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";145 reg = <0x83fb0000 0x4000>;146 interrupts = <6>;147 #dma-cells = <3>;148 fsl,sdma-ram-script-name = "sdma-imx51.bin";149 };150 151...152