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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/qcom,adm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm ADM DMA Controller8 9maintainers:10 - Christian Marangi <ansuelsmth@gmail.com>11 - Bjorn Andersson <bjorn.andersson@linaro.org>12 13description: |14 QCOM ADM DMA controller provides DMA capabilities for15 peripheral buses such as NAND and SPI.16 17properties:18 compatible:19 const: qcom,adm20 21 reg:22 maxItems: 123 24 interrupts:25 maxItems: 126 27 "#dma-cells":28 const: 129 30 clocks:31 items:32 - description: phandle to the core clock33 - description: phandle to the iface clock34 35 clock-names:36 items:37 - const: core38 - const: iface39 40 resets:41 items:42 - description: phandle to the clk reset43 - description: phandle to the pbus reset44 - description: phandle to the c0 reset45 - description: phandle to the c1 reset46 - description: phandle to the c2 reset47 48 reset-names:49 items:50 - const: clk51 - const: pbus52 - const: c053 - const: c154 - const: c255 56 qcom,ee:57 $ref: /schemas/types.yaml#/definitions/uint3258 description: indicates the security domain identifier used in the secure world.59 minimum: 060 maximum: 25561 62required:63 - compatible64 - reg65 - interrupts66 - "#dma-cells"67 - clocks68 - clock-names69 - resets70 - reset-names71 - qcom,ee72 73additionalProperties: false74 75examples:76 - |77 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>78 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>79 80 adm_dma: dma-controller@18300000 {81 compatible = "qcom,adm";82 reg = <0x18300000 0x100000>;83 interrupts = <0 170 0>;84 #dma-cells = <1>;85 86 clocks = <&gcc ADM0_CLK>,87 <&gcc ADM0_PBUS_CLK>;88 clock-names = "core", "iface";89 90 resets = <&gcc ADM0_RESET>,91 <&gcc ADM0_PBUS_RESET>,92 <&gcc ADM0_C0_RESET>,93 <&gcc ADM0_C1_RESET>,94 <&gcc ADM0_C2_RESET>;95 reset-names = "clk", "pbus", "c0", "c1", "c2";96 qcom,ee = <0>;97 };98 99...100