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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies Inc GPI DMA controller8 9maintainers:10  - Vinod Koul <vkoul@kernel.org>11 12description: |13  QCOM GPI DMA controller provides DMA capabilities for14  peripheral buses such as I2C, UART, and SPI.15 16allOf:17  - $ref: dma-controller.yaml#18 19properties:20  compatible:21    oneOf:22      - enum:23          - qcom,sdm845-gpi-dma24          - qcom,sm6350-gpi-dma25      - items:26          - enum:27              - qcom,qcm2290-gpi-dma28              - qcom,qdu1000-gpi-dma29              - qcom,sc7280-gpi-dma30              - qcom,sdx75-gpi-dma31              - qcom,sm6115-gpi-dma32              - qcom,sm6375-gpi-dma33              - qcom,sm8350-gpi-dma34              - qcom,sm8450-gpi-dma35              - qcom,sm8550-gpi-dma36              - qcom,sm8650-gpi-dma37              - qcom,x1e80100-gpi-dma38          - const: qcom,sm6350-gpi-dma39      - items:40          - enum:41              - qcom,sdm670-gpi-dma42              - qcom,sm6125-gpi-dma43              - qcom,sm8150-gpi-dma44              - qcom,sm8250-gpi-dma45          - const: qcom,sdm845-gpi-dma46 47  reg:48    maxItems: 149 50  interrupts:51    description:52      Interrupt lines for each GPI instance53    minItems: 154    maxItems: 1355 56  "#dma-cells":57    const: 358    description: >59      DMA clients must use the format described in dma.txt, giving a phandle60      to the DMA controller plus the following 3 integer cells:61      - channel: if set to 0xffffffff, any available channel will be allocated62        for the client. Otherwise, the exact channel specified will be used.63      - seid: serial id of the client as defined in the SoC documentation.64      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h65 66  iommus:67    maxItems: 168 69  dma-channels:70    maximum: 3171 72  dma-channel-mask:73    maxItems: 174 75  dma-coherent: true76 77required:78  - compatible79  - reg80  - interrupts81  - "#dma-cells"82  - iommus83  - dma-channels84  - dma-channel-mask85 86additionalProperties: false87 88examples:89  - |90    #include <dt-bindings/interrupt-controller/arm-gic.h>91    #include <dt-bindings/dma/qcom-gpi.h>92    gpi_dma0: dma-controller@800000 {93        compatible = "qcom,sdm845-gpi-dma";94        #dma-cells = <3>;95        reg = <0x00800000 0x60000>;96        iommus = <&apps_smmu 0x0016 0x0>;97        dma-channels = <13>;98        dma-channel-mask = <0xfa>;99        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,100                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,101                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,102                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,103                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,104                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,105                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,106                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,107                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,108                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,109                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,110                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,111                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;112    };113 114...115