176 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas R-Car and RZ/G DMA Controller8 9maintainers:10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>11 12allOf:13 - $ref: dma-controller.yaml#14 15properties:16 compatible:17 oneOf:18 - items:19 - enum:20 - renesas,dmac-r8a7742 # RZ/G1H21 - renesas,dmac-r8a7743 # RZ/G1M22 - renesas,dmac-r8a7744 # RZ/G1N23 - renesas,dmac-r8a7745 # RZ/G1E24 - renesas,dmac-r8a77470 # RZ/G1C25 - renesas,dmac-r8a774a1 # RZ/G2M26 - renesas,dmac-r8a774b1 # RZ/G2N27 - renesas,dmac-r8a774c0 # RZ/G2E28 - renesas,dmac-r8a774e1 # RZ/G2H29 - renesas,dmac-r8a7790 # R-Car H230 - renesas,dmac-r8a7791 # R-Car M2-W31 - renesas,dmac-r8a7792 # R-Car V2H32 - renesas,dmac-r8a7793 # R-Car M2-N33 - renesas,dmac-r8a7794 # R-Car E234 - renesas,dmac-r8a7795 # R-Car H335 - renesas,dmac-r8a7796 # R-Car M3-W36 - renesas,dmac-r8a77961 # R-Car M3-W+37 - renesas,dmac-r8a77965 # R-Car M3-N38 - renesas,dmac-r8a77970 # R-Car V3M39 - renesas,dmac-r8a77980 # R-Car V3H40 - renesas,dmac-r8a77990 # R-Car E341 - renesas,dmac-r8a77995 # R-Car D342 - const: renesas,rcar-dmac43 44 - items:45 - enum:46 - renesas,dmac-r8a779a0 # R-Car V3U47 - renesas,dmac-r8a779f0 # R-Car S4-848 - renesas,dmac-r8a779g0 # R-Car V4H49 - renesas,dmac-r8a779h0 # R-Car V4M50 - const: renesas,rcar-gen4-dmac # R-Car Gen451 52 reg: true53 54 interrupts:55 minItems: 956 maxItems: 1757 58 interrupt-names:59 minItems: 960 items:61 - const: error62 - pattern: "^ch([0-9]|1[0-5])$"63 - pattern: "^ch([0-9]|1[0-5])$"64 - pattern: "^ch([0-9]|1[0-5])$"65 - pattern: "^ch([0-9]|1[0-5])$"66 - pattern: "^ch([0-9]|1[0-5])$"67 - pattern: "^ch([0-9]|1[0-5])$"68 - pattern: "^ch([0-9]|1[0-5])$"69 - pattern: "^ch([0-9]|1[0-5])$"70 - pattern: "^ch([0-9]|1[0-5])$"71 - pattern: "^ch([0-9]|1[0-5])$"72 - pattern: "^ch([0-9]|1[0-5])$"73 - pattern: "^ch([0-9]|1[0-5])$"74 - pattern: "^ch([0-9]|1[0-5])$"75 - pattern: "^ch([0-9]|1[0-5])$"76 - pattern: "^ch([0-9]|1[0-5])$"77 - pattern: "^ch([0-9]|1[0-5])$"78 79 clocks:80 maxItems: 181 82 clock-names:83 items:84 - const: fck85 86 '#dma-cells':87 const: 188 description:89 The cell specifies the MID/RID of the DMAC port connected to90 the DMA client.91 92 dma-channels:93 minimum: 894 maximum: 1695 96 dma-channel-mask: true97 98 iommus:99 minItems: 8100 maxItems: 16101 102 power-domains:103 maxItems: 1104 105 resets:106 maxItems: 1107 108required:109 - compatible110 - reg111 - interrupts112 - interrupt-names113 - clocks114 - clock-names115 - '#dma-cells'116 - dma-channels117 - power-domains118 - resets119 120if:121 properties:122 compatible:123 contains:124 enum:125 - renesas,rcar-gen4-dmac126then:127 properties:128 reg:129 items:130 - description: Base register block131 - description: Channel register block132else:133 properties:134 reg:135 maxItems: 1136 137additionalProperties: false138 139examples:140 - |141 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>142 #include <dt-bindings/interrupt-controller/arm-gic.h>143 #include <dt-bindings/power/r8a7790-sysc.h>144 145 dmac0: dma-controller@e6700000 {146 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";147 reg = <0xe6700000 0x20000>;148 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,149 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,150 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,151 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,152 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,153 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,154 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,155 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,156 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,157 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,158 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,159 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,160 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,161 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,162 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,163 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;164 interrupt-names = "error",165 "ch0", "ch1", "ch2", "ch3",166 "ch4", "ch5", "ch6", "ch7",167 "ch8", "ch9", "ch10", "ch11",168 "ch12", "ch13", "ch14";169 clocks = <&cpg CPG_MOD 219>;170 clock-names = "fck";171 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;172 resets = <&cpg 219>;173 #dma-cells = <1>;174 dma-channels = <15>;175 };176