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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: SiFive Unleashed Rev C000 Platform DMA8 9maintainers:10 - Green Wan <green.wan@sifive.com>11 - Palmer Debbelt <palmer@sifive.com>12 - Paul Walmsley <paul.walmsley@sifive.com>13 14description: |15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 416 channels. Each channel has 2 interrupts. One is for DMA done and17 the other is for DME error.18 19 In different SoC, DMA could be attached to different IRQ line.20 DT file need to be changed to meet the difference. For technical21 doc,22 23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf24 25allOf:26 - $ref: dma-controller.yaml#27 28properties:29 compatible:30 items:31 - enum:32 - microchip,mpfs-pdma33 - sifive,fu540-c000-pdma34 - const: sifive,pdma035 description:36 Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".37 Supported compatible strings are -38 "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the39 SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block40 with no chip integration tweaks.41 42 reg:43 maxItems: 144 45 interrupts:46 minItems: 147 maxItems: 848 49 dma-channels:50 description: For backwards-compatibility, the default value is 451 minimum: 152 maximum: 453 default: 454 55 '#dma-cells':56 const: 157 58required:59 - compatible60 - reg61 - interrupts62 63unevaluatedProperties: false64 65examples:66 - |67 dma-controller@3000000 {68 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";69 reg = <0x3000000 0x8000>;70 dma-channels = <4>;71 interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;72 #dma-cells = <1>;73 };74 75...76