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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Synopsys DesignWare AXI DMA Controller8 9maintainers:10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>11 12description:13 Synopsys DesignWare AXI DMA Controller DT Binding14 15allOf:16 - $ref: dma-controller.yaml#17 18properties:19 compatible:20 enum:21 - snps,axi-dma-1.01a22 - intel,kmb-axi-dma23 - starfive,jh7110-axi-dma24 - starfive,jh8100-axi-dma25 26 reg:27 minItems: 128 items:29 - description: Address range of the DMAC registers30 - description: Address range of the DMAC APB registers31 32 reg-names:33 items:34 - const: axidma_ctrl_regs35 - const: axidma_apb_regs36 37 interrupts:38 description:39 If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this40 will be per-channel interrupts. Otherwise, this is a single combined IRQ41 for all channels.42 minItems: 143 maxItems: 844 45 clocks:46 items:47 - description: Bus Clock48 - description: Module Clock49 50 clock-names:51 items:52 - const: core-clk53 - const: cfgr-clk54 55 '#dma-cells':56 const: 157 58 dma-channels:59 minimum: 160 maximum: 861 62 resets:63 minItems: 164 maxItems: 265 66 snps,dma-masters:67 description: |68 Number of AXI masters supported by the hardware.69 $ref: /schemas/types.yaml#/definitions/uint3270 enum: [1, 2]71 72 snps,data-width:73 description: |74 AXI data width supported by hardware.75 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)76 $ref: /schemas/types.yaml#/definitions/uint3277 enum: [0, 1, 2, 3, 4, 5, 6]78 79 snps,priority:80 description: |81 Channel priority specifier associated with the DMA channels.82 $ref: /schemas/types.yaml#/definitions/uint32-array83 minItems: 184 maxItems: 885 86 snps,block-size:87 description: |88 Channel block size specifier associated with the DMA channels.89 $ref: /schemas/types.yaml#/definitions/uint32-array90 minItems: 191 maxItems: 892 93 snps,axi-max-burst-len:94 description: |95 Restrict master AXI burst length by value specified in this property.96 If this property is missing the maximum AXI burst length supported by97 DMAC is used.98 $ref: /schemas/types.yaml#/definitions/uint3299 minimum: 1100 maximum: 256101 102required:103 - compatible104 - reg105 - clocks106 - clock-names107 - interrupts108 - '#dma-cells'109 - dma-channels110 - snps,dma-masters111 - snps,data-width112 - snps,priority113 - snps,block-size114 115if:116 properties:117 compatible:118 contains:119 enum:120 - starfive,jh7110-axi-dma121then:122 properties:123 resets:124 minItems: 2125 items:126 - description: AXI reset line127 - description: AHB reset line128 - description: module reset129else:130 properties:131 resets:132 maxItems: 1133 134additionalProperties: false135 136examples:137 - |138 #include <dt-bindings/interrupt-controller/arm-gic.h>139 #include <dt-bindings/interrupt-controller/irq.h>140 /* example with snps,dw-axi-dmac */141 dma-controller@80000 {142 compatible = "snps,axi-dma-1.01a";143 reg = <0x80000 0x400>;144 clocks = <&core_clk>, <&cfgr_clk>;145 clock-names = "core-clk", "cfgr-clk";146 interrupt-parent = <&intc>;147 interrupts = <27>;148 #dma-cells = <1>;149 dma-channels = <4>;150 snps,dma-masters = <2>;151 snps,data-width = <3>;152 snps,block-size = <4096 4096 4096 4096>;153 snps,priority = <0 1 2 3>;154 snps,axi-max-burst-len = <16>;155 };156