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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ST-Ericsson DMA40 DMA Engine8 9maintainers:10 - Linus Walleij <linus.walleij@linaro.org>11 12allOf:13 - $ref: dma-controller.yaml#14 15properties:16 "#dma-cells":17 const: 318 description: |19 The first cell is the unique device channel number as indicated by this20 table for DB8500 which is the only ASIC known to use DMA40:21 22 0: SPI controller 023 1: SD/MMC controller 0 (unused)24 2: SD/MMC controller 1 (unused)25 3: SD/MMC controller 2 (unused)26 4: I2C port 127 5: I2C port 328 6: I2C port 229 7: I2C port 430 8: Synchronous Serial Port SSP031 9: Synchronous Serial Port SSP132 10: Multi-Channel Display Engine MCDE RX33 11: UART port 234 12: UART port 135 13: UART port 036 14: Multirate Serial Port MSP237 15: I2C port 038 16: USB OTG in/out endpoints 7 & 1539 17: USB OTG in/out endpoints 6 & 1440 18: USB OTG in/out endpoints 5 & 1341 19: USB OTG in/out endpoints 4 & 1242 20: SLIMbus or HSI channel 043 21: SLIMbus or HSI channel 144 22: SLIMbus or HSI channel 245 23: SLIMbus or HSI channel 346 24: Multimedia DSP SXA047 25: Multimedia DSP SXA148 26: Multimedia DSP SXA249 27: Multimedia DSP SXA350 28: SD/MMC controller 251 29: SD/MMC controller 052 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v253 31: MSP port 0 or SLIMbus channel 054 32: SD/MMC controller 155 33: SPI controller 256 34: i2c3 RX2 TX257 35: SPI controller 158 36: USB OTG in/out endpoints 3 & 1159 37: USB OTG in/out endpoints 2 & 1060 38: USB OTG in/out endpoints 1 & 961 39: USB OTG in/out endpoints 862 40: SPI controller 363 41: SD/MMC controller 364 42: SD/MMC controller 465 43: SD/MMC controller 566 44: Multimedia DSP SXA467 45: Multimedia DSP SXA568 46: SLIMbus channel 8 or Multimedia DSP SXA669 47: SLIMbus channel 9 or Multimedia DSP SXA770 48: Crypto Accelerator 171 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX72 50: Hash Accelerator 1 TX73 51: memcpy TX (to be used by the DMA driver for memcpy operations)74 52: SLIMbus or HSI channel 475 53: SLIMbus or HSI channel 576 54: SLIMbus or HSI channel 677 55: SLIMbus or HSI channel 778 56: memcpy (to be used by the DMA driver for memcpy operations)79 57: memcpy (to be used by the DMA driver for memcpy operations)80 58: memcpy (to be used by the DMA driver for memcpy operations)81 59: memcpy (to be used by the DMA driver for memcpy operations)82 60: memcpy (to be used by the DMA driver for memcpy operations)83 61: Crypto Accelerator 084 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX85 63: Hash Accelerator 0 TX86 87 The second cell is the DMA request line number. This is only used when88 a fixed channel is allocated, and indicated by setting bit 3 in the89 flags field (see below).90 91 The third cell is a 32bit flags bitfield with the following possible92 bits set:93 0x00000001 (bit 0) - mode:94 Logical channel when unset95 Physical channel when set96 0x00000002 (bit 1) - direction:97 Memory to Device when unset98 Device to Memory when set99 0x00000004 (bit 2) - endianness:100 Little endian when unset101 Big endian when set102 0x00000008 (bit 3) - use fixed channel:103 Use automatic channel selection when unset104 Use DMA request line number when set105 0x00000010 (bit 4) - set channel as high priority:106 Normal priority when unset107 High priority when set108 109 compatible:110 items:111 - const: stericsson,db8500-dma40112 - const: stericsson,dma40113 114 reg:115 oneOf:116 - items:117 - description: DMA40 memory base118 - items:119 - description: DMA40 memory base120 - description: LCPA memory base, deprecated, use eSRAM pool instead121 deprecated: true122 123 124 reg-names:125 oneOf:126 - items:127 - const: base128 - items:129 - const: base130 - const: lcpa131 deprecated: true132 133 interrupts:134 maxItems: 1135 136 clocks:137 maxItems: 1138 139 sram:140 $ref: /schemas/types.yaml#/definitions/phandle-array141 description: A phandle array with inner size 1 (no arg cells).142 First phandle is the LCPA (Logical Channel Parameter Address) memory.143 Second phandle is the LCLA (Logical Channel Link base Address) memory.144 maxItems: 2145 items:146 maxItems: 1147 148 memcpy-channels:149 $ref: /schemas/types.yaml#/definitions/uint32-array150 description: Array of u32 elements indicating which channels on the DMA151 engine are eligible for memcpy transfers152 153required:154 - "#dma-cells"155 - compatible156 - reg157 - interrupts158 - clocks159 - sram160 - memcpy-channels161 162additionalProperties: false163 164examples:165 - |166 #include <dt-bindings/interrupt-controller/irq.h>167 #include <dt-bindings/interrupt-controller/arm-gic.h>168 #include <dt-bindings/mfd/dbx500-prcmu.h>169 dma-controller@801c0000 {170 compatible = "stericsson,db8500-dma40", "stericsson,dma40";171 reg = <0x801c0000 0x1000>;172 reg-names = "base";173 sram = <&lcpa>, <&lcla>;174 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;175 #dma-cells = <3>;176 memcpy-channels = <56 57 58 59 60>;177 clocks = <&prcmu_clk PRCMU_DMACLK>;178 };179...180