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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STMicroelectronics STM32 DMA3 Controller8 9description: |10 The STM32 DMA3 is a direct memory access controller with different features11 depending on its hardware configuration.12 It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High13 Performance).14 Its hardware configuration registers allow to dynamically expose its features.15 16 GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA.17 GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA.18 19 Bindings are generic for these 3 STM32 DMA3 configurations.20 21 DMA clients connected to the STM32 DMA3 controller must use the format22 described in "#dma-cells" property description below, using a three-cell23 specifier for each channel.24 25maintainers:26 - Amelie Delaunay <amelie.delaunay@foss.st.com>27 28allOf:29 - $ref: /schemas/dma/dma-controller.yaml#30 31properties:32 compatible:33 const: st,stm32mp25-dma334 35 reg:36 maxItems: 137 38 interrupts:39 minItems: 440 maxItems: 1641 description:42 Should contain all of the per-channel DMA interrupts in ascending order43 with respect to the DMA channel index.44 45 clocks:46 maxItems: 147 48 resets:49 maxItems: 150 51 power-domains:52 maxItems: 153 54 "#dma-cells":55 const: 356 description: |57 Specifies the number of cells needed to provide DMA controller specific58 information.59 The first cell is the request line number.60 The second cell is a 32-bit mask specifying the DMA channel requirements:61 -bit 0-1: The priority level62 0x0: low priority, low weight63 0x1: low priority, mid weight64 0x2: low priority, high weight65 0x3: high priority66 -bit 4-7: The FIFO requirement for queuing source/destination transfers67 0x0: no FIFO requirement/any channel can fit68 0x2: FIFO of 8 bytes (2^2+1)69 0x4: FIFO of 32 bytes (2^4+1)70 0x6: FIFO of 128 bytes (2^6+1)71 0x7: FIFO of 256 bytes (2^7+1)72 The third cell is a 32-bit mask specifying the DMA transfer requirements:73 -bit 0: The source incrementing burst74 0x0: fixed burst75 0x1: contiguously incremented burst76 -bit 1: The source allocated port77 0x0: port 0 is allocated to the source transfer78 0x1: port 1 is allocated to the source transfer79 -bit 4: The destination incrementing burst80 0x0: fixed burst81 0x1: contiguously incremented burst82 -bit 5: The destination allocated port83 0x0: port 0 is allocated to the destination transfer84 0x1: port 1 is allocated to the destination transfer85 -bit 8: The type of hardware request86 0x0: burst87 0x1: block88 -bit 9: The control mode89 0x0: DMA controller control mode90 0x1: peripheral control mode91 -bit 12-13: The transfer complete event mode92 0x0: at block level, transfer complete event is generated at the end93 of a block94 0x2: at LLI level, the transfer complete event is generated at the end95 of the LLI transfer96 including the update of the LLI if any97 0x3: at channel level, the transfer complete event is generated at the98 end of the last LLI99 100required:101 - compatible102 - reg103 - interrupts104 - clocks105 - "#dma-cells"106 107unevaluatedProperties: false108 109examples:110 - |111 #include <dt-bindings/interrupt-controller/arm-gic.h>112 #include <dt-bindings/clock/st,stm32mp25-rcc.h>113 dma-controller@40400000 {114 compatible = "st,stm32mp25-dma3";115 reg = <0x40400000 0x1000>;116 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,117 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,118 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,119 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,120 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,121 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,122 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,123 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,124 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,125 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,126 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,127 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,128 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,129 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,130 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,131 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;132 clocks = <&rcc CK_BUS_HPDMA1>;133 #dma-cells = <3>;134 };135...136