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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STMicroelectronics STM32 MDMA Controller8 9description: |10 The STM32 MDMA is a general-purpose direct memory access controller capable of11 supporting 64 independent DMA channels with 256 HW requests.12 DMA clients connected to the STM32 MDMA controller must use the format13 described in the dma.txt file, using a five-cell specifier for each channel:14 a phandle to the MDMA controller plus the following five integer cells:15 1. The request line number16 2. The priority level17 0x0: Low18 0x1: Medium19 0x2: High20 0x3: Very high21 3. A 32bit mask specifying the DMA channel configuration22 -bit 0-1: Source increment mode23 0x0: Source address pointer is fixed24 0x2: Source address pointer is incremented after each data transfer25 0x3: Source address pointer is decremented after each data transfer26 -bit 2-3: Destination increment mode27 0x0: Destination address pointer is fixed28 0x2: Destination address pointer is incremented after each data transfer29 0x3: Destination address pointer is decremented after each data transfer30 -bit 8-9: Source increment offset size31 0x0: byte (8bit)32 0x1: half-word (16bit)33 0x2: word (32bit)34 0x3: double-word (64bit)35 -bit 10-11: Destination increment offset size36 0x0: byte (8bit)37 0x1: half-word (16bit)38 0x2: word (32bit)39 0x3: double-word (64bit)40 -bit 25-18: The number of bytes to be transferred in a single transfer41 (min = 1 byte, max = 128 bytes)42 -bit 29:28: Trigger Mode43 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)44 0x1: Each MDMA request triggers a block transfer (max 64K bytes)45 0x2: Each MDMA request triggers a repeated block transfer46 0x3: Each MDMA request triggers a linked list transfer47 4. A 32bit value specifying the register to be used to acknowledge the request48 if no HW ack signal is used by the MDMA client49 5. A 32bit mask specifying the value to be written to acknowledge the request50 if no HW ack signal is used by the MDMA client51 52maintainers:53 - Amelie Delaunay <amelie.delaunay@foss.st.com>54 55allOf:56 - $ref: /schemas/dma/dma-controller.yaml#57 58properties:59 "#dma-cells":60 const: 561 62 compatible:63 const: st,stm32h7-mdma64 65 reg:66 maxItems: 167 68 clocks:69 maxItems: 170 71 interrupts:72 maxItems: 173 74 resets:75 maxItems: 176 77 st,ahb-addr-masks:78 $ref: /schemas/types.yaml#/definitions/uint32-array79 description: Array of u32 mask to list memory devices addressed via AHB bus.80 81required:82 - compatible83 - reg84 - clocks85 - interrupts86 87unevaluatedProperties: false88 89examples:90 - |91 #include <dt-bindings/interrupt-controller/arm-gic.h>92 #include <dt-bindings/clock/stm32mp1-clks.h>93 #include <dt-bindings/reset/stm32mp1-resets.h>94 dma-controller@52000000 {95 compatible = "st,stm32h7-mdma";96 reg = <0x52000000 0x1000>;97 interrupts = <122>;98 clocks = <&timer_clk>;99 resets = <&rcc 992>;100 #dma-cells = <5>;101 dma-channels = <16>;102 dma-requests = <32>;103 st,ahb-addr-masks = <0x20000000>, <0x00000000>;104 };105 106...107