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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2020 Texas Instruments Incorporated3# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>4%YAML 1.25---6$id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#7$schema: http://devicetree.org/meta-schemas/core.yaml#8 9title: Texas Instruments K3 DMSS PKTDMA10 11maintainers:12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>13 14description: |15 The Packet DMA (PKTDMA) is intended to perform similar functions as the packet16 mode channels of K3 UDMA-P.17 PKTDMA only includes Split channels to service PSI-L based peripherals.18 19 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals20 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the21 legacy peripheral.22 23 PDMAs can be configured via PKTDMA split channel's peer registers to match24 with the configuration of the legacy peripheral.25 26allOf:27 - $ref: /schemas/dma/dma-controller.yaml#28 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#29 30properties:31 compatible:32 const: ti,am64-dmss-pktdma33 34 "#dma-cells":35 const: 236 description: |37 The first cell is the PSI-L thread ID of the remote (to PKTDMA) end.38 Valid ranges for thread ID depends on the data movement direction:39 for source thread IDs (rx): 0 - 0x7fff40 for destination thread IDs (tx): 0x8000 - 0xffff41 42 Please refer to the device documentation for the PSI-L thread map and also43 the PSI-L peripheral chapter for the correct thread ID.44 45 The second cell is the ASEL value for the channel46 47 reg:48 minItems: 449 items:50 - description: Packet DMA Control /Status Registers region51 - description: RX Channel Realtime Registers region52 - description: TX Channel Realtime Registers region53 - description: Ring Realtime Registers region54 - description: Ring Configuration Registers region55 - description: TX Configuration Registers region56 - description: RX Configuration Registers region57 - description: RX Flow Configuration Registers region58 59 reg-names:60 minItems: 461 items:62 - const: gcfg63 - const: rchanrt64 - const: tchanrt65 - const: ringrt66 - const: ring67 - const: tchan68 - const: rchan69 - const: rflow70 71 msi-parent: true72 73 ti,sci-rm-range-tchan:74 $ref: /schemas/types.yaml#/definitions/uint32-array75 description: |76 Array of PKTDMA split tx channel resource subtypes for resource allocation77 for this host78 minItems: 179 # Should be enough80 maxItems: 25581 items:82 maximum: 0x3f83 84 ti,sci-rm-range-tflow:85 $ref: /schemas/types.yaml#/definitions/uint32-array86 description: |87 Array of PKTDMA split tx flow resource subtypes for resource allocation88 for this host89 minItems: 190 # Should be enough91 maxItems: 25592 items:93 maximum: 0x3f94 95 ti,sci-rm-range-rchan:96 $ref: /schemas/types.yaml#/definitions/uint32-array97 description: |98 Array of PKTDMA split rx channel resource subtypes for resource allocation99 for this host100 minItems: 1101 # Should be enough102 maxItems: 255103 items:104 maximum: 0x3f105 106 ti,sci-rm-range-rflow:107 $ref: /schemas/types.yaml#/definitions/uint32-array108 description: |109 Array of PKTDMA split rx flow resource subtypes for resource allocation110 for this host111 minItems: 1112 # Should be enough113 maxItems: 255114 items:115 maximum: 0x3f116 117required:118 - compatible119 - "#dma-cells"120 - reg121 - reg-names122 - msi-parent123 - ti,sci124 - ti,sci-dev-id125 - ti,sci-rm-range-tchan126 - ti,sci-rm-range-tflow127 - ti,sci-rm-range-rchan128 - ti,sci-rm-range-rflow129 130unevaluatedProperties: false131 132examples:133 - |+134 cbass_main {135 #address-cells = <2>;136 #size-cells = <2>;137 138 main_dmss {139 compatible = "simple-mfd";140 #address-cells = <2>;141 #size-cells = <2>;142 dma-ranges;143 ranges;144 145 ti,sci-dev-id = <25>;146 147 main_pktdma: dma-controller@485c0000 {148 compatible = "ti,am64-dmss-pktdma";149 150 reg = <0x0 0x485c0000 0x0 0x100>,151 <0x0 0x4a800000 0x0 0x20000>,152 <0x0 0x4aa00000 0x0 0x40000>,153 <0x0 0x4b800000 0x0 0x400000>,154 <0x0 0x485e0000 0x0 0x20000>,155 <0x0 0x484a0000 0x0 0x4000>,156 <0x0 0x484c0000 0x0 0x2000>,157 <0x0 0x48430000 0x0 0x4000>;158 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",159 "ring", "tchan", "rchan", "rflow";160 161 msi-parent = <&inta_main_dmss>;162 #dma-cells = <2>;163 164 ti,sci = <&dmsc>;165 ti,sci-dev-id = <30>;166 167 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */168 <0x24>, /* CPSW_TX_CHAN */169 <0x25>, /* SAUL_TX_0_CHAN */170 <0x26>, /* SAUL_TX_1_CHAN */171 <0x27>, /* ICSSG_0_TX_CHAN */172 <0x28>; /* ICSSG_1_TX_CHAN */173 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */174 <0x11>, /* RING_CPSW_TX_CHAN */175 <0x12>, /* RING_SAUL_TX_0_CHAN */176 <0x13>, /* RING_SAUL_TX_1_CHAN */177 <0x14>, /* RING_ICSSG_0_TX_CHAN */178 <0x15>; /* RING_ICSSG_1_TX_CHAN */179 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */180 <0x2b>, /* CPSW_RX_CHAN */181 <0x2d>, /* SAUL_RX_0_CHAN */182 <0x2f>, /* SAUL_RX_1_CHAN */183 <0x31>, /* SAUL_RX_2_CHAN */184 <0x33>, /* SAUL_RX_3_CHAN */185 <0x35>, /* ICSSG_0_RX_CHAN */186 <0x37>; /* ICSSG_1_RX_CHAN */187 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */188 <0x2c>, /* FLOW_CPSW_RX_CHAN */189 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */190 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */191 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */192 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */193 };194 };195 };196