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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2019 Texas Instruments Incorporated3# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>4%YAML 1.25---6$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#7$schema: http://devicetree.org/meta-schemas/core.yaml#8 9title: Texas Instruments K3 NAVSS Unified DMA10 11maintainers:12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>13 14description: |15 The UDMA-P is intended to perform similar (but significantly upgraded)16 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P17 module supports the transmission and reception of various packet types.18 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA19 data structure compliant packets to/from smaller data blocks that are natively20 compatible with the specific requirements of each connected peripheral.21 Multiple Tx and Rx channels are provided within the DMA which allow multiple22 segmentation or reassembly operations to be ongoing. The DMA controller23 maintains state information for each of the channels which allows packet24 segmentation and reassembly operations to be time division multiplexed between25 channels in order to share the underlying DMA hardware. An external DMA26 scheduler is used to control the ordering and rate at which this multiplexing27 occurs for Transmit operations. The ordering and rate of Receive operations28 is indirectly controlled by the order in which blocks are pushed into the DMA29 on the Rx PSI-L interface.30 31 The UDMA-P also supports acting as both a UTC and UDMA-C for its internal32 channels. Channels in the UDMA-P can be configured to be either Packet-Based33 or Third-Party channels on a channel by channel basis.34 35 All transfers within NAVSS is done between PSI-L source and destination36 threads.37 The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or38 legacy, non PSI-L native peripherals. In the later case a special, small PDMA39 is tasked to act as a bridge between the PSI-L fabric and the legacy40 peripheral.41 42 PDMAs can be configured via UDMAP peer registers to match with the43 configuration of the legacy peripheral.44 45allOf:46 - $ref: ../dma-controller.yaml#47 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#48 49properties:50 "#dma-cells":51 minimum: 152 maximum: 253 description: |54 The cell is the PSI-L thread ID of the remote (to UDMAP) end.55 Valid ranges for thread ID depends on the data movement direction:56 for source thread IDs (rx): 0 - 0x7fff57 for destination thread IDs (tx): 0x8000 - 0xffff58 59 Please refer to the device documentation for the PSI-L thread map and also60 the PSI-L peripheral chapter for the correct thread ID.61 62 When #dma-cells is 2, the second parameter is the channel ATYPE.63 64 compatible:65 enum:66 - ti,am654-navss-main-udmap67 - ti,am654-navss-mcu-udmap68 - ti,j721e-navss-main-udmap69 - ti,j721e-navss-mcu-udmap70 71 reg:72 minItems: 373 items:74 - description: UDMA-P Control /Status Registers region75 - description: RX Channel Realtime Registers region76 - description: TX Channel Realtime Registers region77 - description: TX Configuration Registers region78 - description: RX Configuration Registers region79 - description: RX Flow Configuration Registers region80 81 reg-names:82 minItems: 383 items:84 - const: gcfg85 - const: rchanrt86 - const: tchanrt87 - const: tchan88 - const: rchan89 - const: rflow90 91 msi-parent: true92 93 ti,ringacc:94 description: phandle to the ring accelerator node95 $ref: /schemas/types.yaml#/definitions/phandle96 97 ti,sci-rm-range-tchan:98 description: |99 Array of UDMA tchan resource subtypes for resource allocation for this100 host101 $ref: /schemas/types.yaml#/definitions/uint32-array102 minItems: 1103 # Should be enough104 maxItems: 255105 106 ti,sci-rm-range-rchan:107 description: |108 Array of UDMA rchan resource subtypes for resource allocation for this109 host110 $ref: /schemas/types.yaml#/definitions/uint32-array111 minItems: 1112 # Should be enough113 maxItems: 255114 115 ti,sci-rm-range-rflow:116 description: |117 Array of UDMA rflow resource subtypes for resource allocation for this118 host119 $ref: /schemas/types.yaml#/definitions/uint32-array120 minItems: 1121 # Should be enough122 maxItems: 255123 124required:125 - compatible126 - "#dma-cells"127 - reg128 - reg-names129 - msi-parent130 - ti,sci131 - ti,sci-dev-id132 - ti,ringacc133 - ti,sci-rm-range-tchan134 - ti,sci-rm-range-rchan135 - ti,sci-rm-range-rflow136 137if:138 properties:139 "#dma-cells":140 const: 2141then:142 properties:143 ti,udma-atype:144 description: ATYPE value which should be used by non slave channels145 $ref: /schemas/types.yaml#/definitions/uint32146 147 required:148 - ti,udma-atype149 150unevaluatedProperties: false151 152examples:153 - |+154 cbass_main {155 #address-cells = <2>;156 #size-cells = <2>;157 158 cbass_main_navss: navss@30800000 {159 compatible = "simple-mfd";160 #address-cells = <2>;161 #size-cells = <2>;162 dma-coherent;163 dma-ranges;164 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;165 166 ti,sci-dev-id = <118>;167 168 main_udmap: dma-controller@31150000 {169 compatible = "ti,am654-navss-main-udmap";170 reg = <0x0 0x31150000 0x0 0x100>,171 <0x0 0x34000000 0x0 0x100000>,172 <0x0 0x35000000 0x0 0x100000>,173 <0x0 0x30b00000 0x0 0x20000>,174 <0x0 0x30c00000 0x0 0x8000>,175 <0x0 0x30d00000 0x0 0x4000>;176 reg-names = "gcfg", "rchanrt", "tchanrt", "tchan", "rchan", "rflow";177 #dma-cells = <1>;178 179 ti,ringacc = <&ringacc>;180 181 msi-parent = <&inta_main_udmass>;182 183 ti,sci = <&dmsc>;184 ti,sci-dev-id = <188>;185 186 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */187 <0x2>; /* TX_CHAN */188 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */189 <0x5>; /* RX_CHAN */190 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */191 };192 };193 };194