91 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx ZynqMP DMA Engine8 9description: |10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,11 memory to device and device to memory transfers. It also has flow12 control and rate control support for slave/peripheral dma access.13 14maintainers:15 - Michael Tretter <m.tretter@pengutronix.de>16 - Harini Katakam <harini.katakam@amd.com>17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>18 19allOf:20 - $ref: ../dma-controller.yaml#21 22properties:23 "#dma-cells":24 const: 125 26 compatible:27 enum:28 - amd,versal2-dma-1.029 - xlnx,zynqmp-dma-1.030 31 reg:32 description: memory map for gdma/adma module access33 maxItems: 134 35 interrupts:36 description: DMA channel interrupt37 maxItems: 138 39 clocks:40 description: input clocks41 minItems: 242 maxItems: 243 44 clock-names:45 items:46 - const: clk_main47 - const: clk_apb48 49 xlnx,bus-width:50 $ref: /schemas/types.yaml#/definitions/uint3251 enum:52 - 6453 - 12854 description: AXI bus width in bits55 56 iommus:57 maxItems: 158 59 power-domains:60 maxItems: 161 62 dma-coherent:63 description: present if dma operations are coherent64 65required:66 - "#dma-cells"67 - compatible68 - reg69 - interrupts70 - clocks71 - clock-names72 - xlnx,bus-width73 74additionalProperties: false75 76examples:77 - |78 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>79 80 fpd_dma_chan1: dma-controller@fd500000 {81 compatible = "xlnx,zynqmp-dma-1.0";82 reg = <0xfd500000 0x1000>;83 interrupt-parent = <&gic>;84 interrupts = <0 117 0x4>;85 #dma-cells = <1>;86 clock-names = "clk_main", "clk_apb";87 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;88 xlnx,bus-width = <128>;89 dma-coherent;90 };91